Execution Model to Reduce the Interference of Shared Memory in ARINC 653 Compliant Multicore RTOS

Sihyeong Park
Sihyeong Park
Mi-Young Kwon
Mi-Young Kwon
Hoon-Kyu Kim
Hoon-Kyu Kim

APPLIED SCIENCES-BASEL, pp. 24642020.

Cited by: 0|Views8

Abstract:

Multicore architecture is applied to contemporary avionics systems to deal with complex tasks. However, multicore architectures can cause interference by contention because the cores share hardware resources. This interference reduces the predictable execution time of safety-critical systems, such as avionics systems. To reduce this inter...More

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