Impact of On-Chip Interconnect on the Performance of 3-D Integrated Circuits With Through Silicon Vias: Part I
IEEE Transactions on Electron Devices, pp. 2503-2509, 2016.
Circuit-level models are developed to determine the upper bound on the performance of a 3-D IC link with through silicon vias (TSVs). It is shown that the performance of a 3-D link is limited not only by the on-chip interconnect RC, driver resistance, and TSV capacitance, but also by the current carrying capacity of the on-chip wires conn...More
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