Benchmarking and Optimization of Spintronic Memory Arrays

Yu-Ching Liao
Yu-Ching Liao

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, pp. 9-17, 2020.

Cited by: 0|Bibtex|Views4|DOI:https://doi.org/10.1109/JXCDC.2020.2999270
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Abstract:

In this article, we present a cross-layer optimization and benchmarking of various spintronic memory devices, including spin-transfer-torque magnetic random access memory (STT-MRAM), spin-orbit-torque (SOT) MRAM, voltage-controlled exchange coupling (VCEC) MRAM, and magnetoelectric (ME) MRAM. Various material, device, and circuit paramete...More

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