FPGA developments for the SPARTA project: Part 3

The European Southern Observatory (ESO) and Durham University's Centre for Advanced Instrumentation (CfAI) have progressed the 'Standard Platform for Adaptive optics Real-Time Applications' (SPARTA) to a preliminary design which successfully passed review in July 07. SPARTA's Real-Time Control box contains a mixture of processors, Digital Signal Processors and Field Programmable Gate Arrays (FPGA). The card selected in the design to host SPARTA's FPGA based Wavefront Processing Unit (WPU) is the VMETRO dual processor, dual FPGA VPF1 board. CfAl benchmarked this card along with the VMETRO Zero Latency Switch Card to assess their suitability for the SPARTA design. The VPF1 benchmark tests summarised in this paper includes: transfering data between FPGAs, between the FPGAs and PPCs (with and without the TransComm controller), from PPC to an external host via Ethernet and finally from the FPGA optical transceiver using CfAI's Serial Front Panel Data Port (sFPDP) core. Results show that the VPF1 is suitable to use as a WPU host card as the measured 280 MB/s FGPA to PPC TransComm data rates easily cope with SPARTA's maximum requirement of 30 MB/s. Using the VPFl as a "back-end" controller introduces a latency of 17 mu s, which is greater than the original requirements of 12 mu s but still acceptable. The conclusion of the benchmarking tests and the design review is that the VPF1 and Zero Latency Switch have been selected for use in SPARTA.