What is the future of sub-100nm CMOS: Ultrashallow junctions or ultrathin SOI?

Planar CMOS transistors on bulk silicon wafers are expected to reach their limits at gate sizes about 50nm in 2005-06. Many of the process and materials constraints that combine to force this change in technology path are relaxed or removed for CMOS devices fabricated on SOI wafers. This article outlines the principal issues limiting junction formation for sub-100nm CMOS on bulk silicon and presents an alternative roadmap using SOI wafers. An SOI wafer fabrication technology is described that provides a room temperature, atomic layer cleaving process with unprecedented levels of control on silicon layer thickness, as well as a clear path for extension towards the ultrathin SOI regime.