Low-Clock-Power Digital Standard Cell IPs for High-Performance Graphics/AI Processors in 10nm CMOS
2020 IEEE Symposium on VLSI Circuits(2020)
摘要
Low-clock-power digital standard cell IPs in 10nm CMOS, featuring low-power shared-clock (LPSC) flip-flops (FFs), LPSC back-to-back (B2B) FFs, and pass-gate (PG) integrated clock gates (ICGs), achieve up to 14%, 45%, and 14% measured clock energy improvements, respectively, by reducing the number of clocked devices over state-of-the-art conventional transmission-gate (TG) FF and AND ICG circuits. The LPSC FF achieves a mean worst-case black-hole-time (BHT) improvement of 17ps, while the PG ICG achieves a mean enable/disable setup time improvement of 16ps/15ps, compared to conventional circuits measured at 650mV, 25°C. Power analysis of a graphics processor block with these optimized IPs results in an overall 6% clock power reduction without frequency impact.
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关键词
CMOS,low-clock-power digital standard cell IPs,low-power shared-clock,clocked devices,worst-case black-hole-time improvement,clock power reduction,measured clock energy improvements,low-clock-power digital standard cell IP,high-performance graphics,AI processors,flip-flops,LPSC back-to-back FF,pass-gate,integrated clock gates,transmission-gate FF,AND ICG circuits,mean enable-disable setup time improvement,power analysis,graphics processor block,temperature 25.0 degC,size 10.0 nm,time 16.0 ps,time 15.0 ps,voltage 650.0 mV
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