A 13 Bit 100 MS/s SAR ADC with 74.57 dB SNDR in 14-nm CMOS FinFET

A 13 bit 100 MS/s successive approximation register analog-to-digital converter (SAR ADC) is presented for high-resolution and high-speed applications. In order to reduce comparator noise and improve the speed of comparator, a three-stage comparator based on the inverter is proposed. To reduce the leakage current of the low-Vt transistor, an improved asynchronous control logic with feedback is proposed. An energy-efficient SAR ADC with high sampling rate can be realized with these techniques combined. The prototype is implemented in SMIC 14-nm CMOS FinFET. Simulation result with noise, parasitic capacitance, and other non-ideal effects shows that ADC achieves a low input frequency SNDR/SFDR of 75.13/89.48dB, while the SNDR/SFDR at Nyquist is 74.57/84.42dB without any calibration. The prototype consumes 2.34mW from 0.8-V supply, leading to a Walden figure-of-merit 5.22fJ/conversion-step at Nyquist.