Self-Adjusting Deadtime Generator for High-Efficiency High-Voltage Switched-Mode Power Amplifiers

In this paper, we propose a novel design methodology for a deadtime generator for high-efficiency power amplifiers. It consists of a two-phase non-overlapping clock circuit and level down shifters. A 3% improvement in efficiency is achieved with a maximum efficiency of 94% in a class-D power amplifier circuit. The proposed design generates a deadtime as low as 16.7ns and eliminates the problem of propagation delay mismatch between high side and low side gate drivers. The circuit is implemented in 50V AMS 0.35 mu m CMOS technology. The deadtime generator consumes 16.5 mW, while occupying a total area of 0.068 mm(2).