Variability Evaluation Of 28nm Fd-Soi Technology At Cryogenic Temperatures Down To 100mk For Quantum Computing

Variability of 28nm FD-SOI transistors is evaluated for the first time down to ultra low temperatures (ULT), at T=100mK. High performance is achieved at ULT for short channel transistors, with I-ON>1mA/mu m and I-OFF below the equipment accuracy <1fA, in particular by keeping advantage of forward back biasing (FBB), with the same efficiency from room temperature (RT) down to 100mK. The physical origins of MOSFET mismatch at ULT are studied, highlighting the impact of the charge fluctuations increase on both threshold voltage (V-TH) and current gain factor (beta) variabilities. Besides that, we demonstrated that the increase of V-TH and beta variabilities at low temperature remains reasonably low in comparison to RT values and other CMOS technologies, so that it should not be detrimental to circuit operation in this range of temperatures.