A 12-bit SAR ADC Using Pseudo-Dynamic Weighting C-DAC for Capacitor Error Calibration.

A 12-bit SAR ADC is implemented with bridge capacitor array. A redundant weight method is adopted for decision error tolerance due to parasite, mismatch and incomplete settling. An LMS-based digital calibration is utilized to estimate and correct the weight error among capacitors. A pseudo-dynamic weighting DAC scheme is proposed to reuse the embedded C-DAC in SAR ADC as a reference for calibration. Simulation results show the ADC with conversion rate of 200MS/s achieves an SNDR of 68.0dB using a 28nm CMOS technology, with remarkable improvement after calibration.