A resource-efficient priority scheduler for time-sensitive networking switches

Time-sensitive networking (TSN) supports the integration of standard Ethernet and industrial control networ k by providing differential quality of service (QoS). A priority scheduler is typically the central component of TSN switches for QoS. Furthermore, TSN must deal with various requirements from various domains. As a result, an FPGA-based solution becomes one of the most promising solutions for TSN switches due to its programmability and customizability. But, resource usually becomes a bottleneck in such a solution. This study proposes a flattened-priority approach to develop a new resource-efficient priority scheduler called f-iSLIP by converting the widely used nonpriority scheduler, iSLIP. We implement f-iSLIP in our TSN switches and compare it with previous priority schedulers. It reduces the resource cost of lookup tables (LUTs) by 30–50% on average and the logic latency by 20–30% on average. Moreover, the throughput tests demonstrate that it prefers high priorities with no performance loss.