Design And Analysis Of A Low-Power Ternary Sram

Youngchang Choi,Sunmean Kim,Kyongsu Lee,Seokhyeong Kang

2021 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)（2021）

引用 9|浏览4

暂无评分

摘要

This paper proposes the design of a ternary inverter that uses low current as input voltage is VDD/2. When the supply voltage is set to 1 V, current supplied by a voltage source as an input voltage VDD/2 is reduced by 22.75% from 1.89 mu A to 1.46 mu A. By connecting ternary inverters back-to-back, a trit-storage element is implemented as a ternary SRAM cell. This paper also presents the first verification of read/write schemes that consider noise margins.

查看译文

关键词

read-write schemes,low-power ternary SRAM design,ternary SRAM cell,trit-storage element,voltage source,supply voltage,ternary inverter,voltage 1.0 V,current 1.89 muA to 1.46 muA

AI 理解论文

溯源树

样例

生成溯源树，研究论文发展脉络

Chat Paper

正在生成论文摘要