Exploiting Vitis Framework for Accelerating Sobel Algorithm.

MECO(2021)

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Abstract
Edge detection is one of the most common operations needed in the image processing domain. In this work, alternative implementations of the Sobel algorithm are tested on a ZCU102 Xilinx embedded platform, demonstrating how different optimization techniques can be conveniently configured in Xilinx Vitis environment. We exploit (a) Xilinx Runtime library (XRT) that allows the reprogramming of the reconfigurable logic at real time and (b) the various high-level attributes offered by the OpenCL API for efficient resource allocation in the state-of-the-art Xilinx Ultrascale Multi-Processor System-on-Chips (MPSoC). Specifically, different implementations of the Sobel algorithm (varying the data transfer models and data packing modes) are demonstrated and analyzed. Our experimental results shows that starting from a CPU implementation with 656 ms latency, the frame processing time is reduced to a range between 17 ms and 22 ms depending on the allocated resources, leading to a solution that is up to 38 times faster.
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Key words
Sobel algorithm,OpenCL,Image Processing,Pipeline,FPGA Acceleration,Artificial Intelligence,Xilinx Vitis,Xilinx HLS
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