A 10-core SoC with 20 Fine-Grain Power Domains for Energy-Proportional Data-Parallel Processing over a Wide Voltage and Temperature Range

ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)(2021)

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Abstract
We present Thestral, a 10-core RISC-V chip for energy-proportional parallel computing manufactured in 22 nm FD-SOI technology. Thestral contains a control core and a nine-core compute cluster. Each core features a single-precision floating-point unit (FPU) and an integer processing unit (IPU) and implements custom instruction set architecture (ISA) extensions to improve utilization. The chip featu...
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Key words
Temperature distribution,Power measurement,Power system management,Instruction sets,Europe,Computer architecture,Parallel processing
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