Study of Layout effect on Gate oxide TDDB in sub-16nm FinFET technology

Xiangyu Liu,Yongsheng Sun,Junlin Huang,Changze Liu,Xiaolu Shang

2021 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)（2021）

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摘要

In this work, TDDB characteristic in sub-16nm FinFET technology are investigated by experiments. The Weibull slope β and voltage coefficient n of NMOSFET and PMOSFET are equals to 1.45/0.95 and -30.5/-37.6 based on the results having various stress voltage, respectively. Moreover, since the layout effect of NMOSFET and PMOSFET, the difference in T63 normalized by total device gate oxide...

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关键词

Performance evaluation,Integrated circuit synthesis,Layout,Failure analysis,Voltage,MOSFET circuits,Logic gates

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