An Accurate Process Induced Variability Aware Compact Model-based Circuit Performance Estimation for Design-Technology Co-optimization
IEEE Transactions on Electron Devices(2021)
Key words
Berkeley short-channel igfet model-common multi-gate (BSIM-CMG),design-technology co-optimization (DTCO),fin field-effect transistor (FinFET),line-edge roughness (LER),metal-gate granularity (MGG),process-induced variability (PIV),simulation program with integrated circuit emphasis (SPICE) simulation,static random-access memory (SRAM),technology computer-aided design (TCAD)
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