1.55mW 2GHz ERBW 7b 800MS/s 3-stage Pipelined SAR ADC in 28nm CMOS using a Kickback-Cancelling 7T-Dynamic Residue Amplifier with only 16fF Input Capacitance

Achieving higher effective resolution bandwidth (ERBW) beyond Nyquist frequency is a key design requirement for the slice ADC design in a time-interleaved ADC (TIADC). While SAR ADC is a popular choice for a low-power ADC in advanced CMOS processes, the input capacitance $(\mathrm{C}_{in})$ presented by the front-end capacitive DAC (CDAC) to the ADC input limits achievable signal bandwidth. In con...