A Contention-Free Wordline Supporting Circuit for High Wordline Resistance in Sub-10nm SRAM Designs

A contention-free wordline supporting (CFWLS) circuit is proposed for SRAM in sub-10nm technologies. The CFWLS resolves the problem of performance degradation caused by significant RC delays with increasing wordline interconnect resistance. A low-skewed sensing inverter utilizes a diode-connected PMOS to detect the wordline rising transition with negligible contention. A supporting PMOS supplies charge to the end of the wordline. By using a replica signal of the wordline enable (WLENt), sufficient charge can be supplied during the entire evaluation phase. The proposed CFWLS has a noise-tolerant characteristic because it complements the floating node by using a pull-up path in the sensing inverter. The WL rising time is improved by 48-57% in post-layout simulation compared to the conventional SRAM without a supporting circuit. The clock-to-bitline (half-VDD) delay is also improved by 20%, while the energy and area overheads of CFWLS are only 7% and 1.7%, respectively. In the test-chip measurements, the read delay for a pass is improved by 180ps (16%) in sub-3nm technologies.