Implementation Method of CORDIC Algorithm to Improve DDFS Performance

An improved CORDIC (Coordinated Rotation Digital Computer) algorithm based on small capacity ROM is proposed. The method of angle binary to bipolar recoding eliminates the calculation of the remaining angle and simplifies the calculation of the scaling factor, at the same time, loop iteration and merge iteration reduce the delay of the system. This work implemented a direct digital frequency synthesizer (DDFS) based on this algorithm. By means of four-channel parallel computing, the system clock is reduced to 250MHz and the sampling rate of DDFS is increased to 1GHz. The phase accumulator is optimized with length configurable module and the addition and subtraction configurable Arithmetic Logical Unit (ALU), the frequency of the system clock is increased and the resource consumption is reduced than the original one. This work takes the 24-bit output bit width as an example to analyze the output effect of DDFS. The results indicate that the maximum absolute error of the output cosine in this work is 6.794×10−7 , and it has an order of magnitude improvement compared with the scheme of the same type algorithm; the spurious-free dynamic range (SFDR) is 86.77dB when the DDFS output is maximum up to 350MHz,it is improving 22.09% than the scheme based on the 12-bit ROM. Meanwhile, the consumption of resources is reduced to 73.3% of the original one, and the delay of the output is only 36ns.