Investigation and Modeling of Etching Through Silicon Carbide Vias (TSiCV) for SiC Interposer and Deep SiC Etching for Harsh Environment MEMS by DoE

This article presents prime results on process development and optimization of dry etching of silicon carbide (SiC) for via formation and deep etching for SiC-based microsystems. The investigations and corresponding results of the process developments enable the first realization of a full SiC-based technological demonstrator composed of a SiC-interposer with a flip chip mounted deep etched micro electromechanical system (MEMS) SiC Device. By optimizing the process, etch depth of 200 mu m with an etch rate of up to 2 mu m/min can be achieved for via etching. In addition, a design of experiments (DoEs) with a total of 29 experiments with seven factors was done to characterize the deep etching of large areas into the SiC. Hereby, vertical sidewalls with low micromasking, low microtrenching and an etch rate of up to 4 mu m/min could be achieved. The findings and optimized processes were implemented to develop on the one hand a 200-mu m-thick SiC interposer with copper metallization. On the other hand, a SiC-MEMS Device was manufactured with a deep etched cavity in SiC bulk wafer forming by the end a 50-mu m thin membrane. The results demonstrate the ability of etching monocrystalline SiC with a high etch rate, enabling new fundamental topologies/structures and packaging concepts for harsh environments MEMSs and high-power electronics. The developed etching technologies demonstrate and enable various applications for 3-D Integration with wide bandgap substrates taking advantage of the superior electrical and mechanical properties of SiC.