High-Performance 10-Transistor Adder Cell for Low-Power Applications

Addition is one of the most fundamental arithmetic operations. Any adder in a digital circuit and system can improve the digital system's performance. Adders, for example, are commonly found in the critical path of many ALUs, processors, and digital signal processing chips. As a result, each of these blocks should execute efficiently and precisely on their own, enhancing the overall performance of the system. Optimizing an adder may lead to overall system optimization. A desirable adder meets all the criteria, such as high speed, low-power dissipation, low leakage power, and small footprint. However, because there is a trade-off between the area, power and, speed.Obtaining the finest adder in terms of speed, power dissipation, leakage power, and area consumed would assist the designer in selecting an adder for the given application. Transmission function adder (TFA), 17-transistor adder (17-TA), 14-transistor adder (14-TA), ripple carry adder (RCA), carry lookahead adder (CLA), and carry-select adder are among the new 2-bit adders suggested and compared (CSL). This research presents a comparative analysis and performance evaluation of adders based on latency, power dissipation, PDP, leakage power, area, and EDP. Simulations are being done using HSPICE software at 28-nm technology with a supply voltage range of 0.7-1.1 V. The suggested adder has a minimum delay and is 8.6% faster than CLA, according to simulation results. When compared to the other adders, it uses the minimum area and has the lowest leakage power. The proposed adder has minimum power delay product.