Investigation on Variability of Ferroelectric-Gate Field-Effect Transistor Memory by Random Spatial Distribution of Interface Trap

We investigated the variability of memory window (MW) in ferroelectric-gate field-effect transistor (FeFET) by considering the spatial distribution of the trap density at the ferroelectric layer/interfacial layer (FE/IL) interface. Through technology computer-aided design (TCAD) simulations including calibrated ferroelectric parameters, the variability of ultrathin body (UTB) structured FeFETs by the scaling of IL and channel area was confirmed. It was revealed that the reduction of IL thickness (T _IL ) not only increases mean of MW (μMW) but also decreases standard deviation of MW (σMW). Additionally, by identifying the σMW/μMW sensitivity for the reduction of gate length (L _G ) and channel width (W), it was indicated that W causes the more serious σMW degradation because short channel effects by L _G scaling mitigate the σMW degradation.