A 59-fs-rms 35-GHz PLL with FoM of −241-dB in $0.18-\mu \mathrm{m}$ BiCMOS/SiGe Technology

A wideband and ultra low-noise Phase-Locked Loop (PLL) circuit is designed and implemented in a $0.18\ \mu \mathrm{m}$ BiCMOS/SiGe technology to operate at a nominal frequency of 35.68 GHz. Incorporating a multi-phase phase frequency detector along with a high frequency reference signal, the bandwidth of the PLL was maximized to reduce the phase noise and jitter contribution of the forward path loop components within the frequency band of interest. A multi-phase phase comparator also relaxes the constraints imposed by the sampling nature of the PLL, allowing for a more convenient performance optimization with reduced jitter peaking and more optimal loop characteristics. The PLL was measured to have a Phase Noise of −113.3 dBc/Hz at an offset frequency of 1 MHz, and a total integrated jitter of 59 fs-rms integrated from 1 kHz to 100 MHz, consuming 194.6 mW with a jitter-power FoM −241.6 dB. The power dissipation of the proposed PLL is lower than implementations in similar technology nodes, while obviously higher than designs made in advanced CMOS/FinFET technologies. The PLL has been designed in BiCMOS/SiGe $0.18 \mu \mathrm{m}$ , aiming to be integrated together with power amplifiers in a 3D structure targeted for the next generation 5G systems.