Investigation of Reflow Effect and Empirical Lifetime Modeling on the Board Level Solder Joint Reliability

Generally, in electronic products, semiconductor chips or components are electrically connected to the main boards by a fine pitch solder interconnection through reflow process. In recent years, as the demand for miniaturization and high performance in various applications such as mobile, automotive, AI devices continuously increases, it is more important to secure board level reliability (BLR). In particular, during system assembly, the stress on the solder joint varies according to different temperature conditions and the number of reflow times, which is expected to affect BLR. Normally, for verification of BLR, board level thermal cycling (BLTC) test is usually performed, which is one of the most widely known methods by applying thermo-mechanical stress. In this study, to investigate the influence of reflow condition on the reliability, board level thermal cycling (BLTC) test was performed for LF35 (Sn-1.2Ag-0.5Cu-0.05Ni) solder after pre-treatment for the samples with reflow from 1 to 10 times and peak temperatures of 245 and 260 degrees C. Consequently, Weibull scale parameter which is 63.2% lifetime showed 4.78% decrement per number of reflow times. For each peak temperature of 245 and 260 degrees C, the characteristic lifetime was obtained as 571 and 586cycles, respectively, indicating that there is no significant difference. From the cross-sectional analysis, solder crack was observed on the package side, meaning that the failure occurred from same mechanism for all conditions. Furthermore, as the number of reflow times accumulated, the intermetallic compound (IMC) thickness increased by 4% per cycles, which raised the probability of solder crack due to the expansion of brittle area followed by reduction of solder life. The difference in IMC at 245 and 260 degrees C was only 0.8%, which was consistent with the result of similar lifetime regardless of the peak temperature. Finite element (FE) analysis based on simulation was performed to verify the lifetime trend of solder by the number of reflow times. The simulation results showed that the variation between the experimental and the predicted life is well fitted within 17% as a function of reflow cycles. Furthermore, it is expected that the decrease in lifetime caused by accumulation of reflow can be quantitatively deduced from empirical life model as well as improve the consistency of board level solder joint reliability test by reflection of real field environment.