Trade‐Off Between Multilevel Characteristics and Power Consumption of High‐Aspect‐Ratio Phase‐Change Memory

Storage density improvement is a key challenge for phase‐change memory (PCM) application for storage class memory (SCM). The high‐aspect‐ratio design in confined‐structure PCM enables controllable multilevel cell (MLC) operation. However, the increasing aspect‐ratio will cause too large energy consumption to successfully operate the PCM. The trade‐off of different aspect‐ratio sizes of Ge2Sb2Te5 (GST) nanowires (NWs) is investigated. Through COMSOL simulation and experiments, with the same Reset energy, the limit of aspect‐ratio decreases with increasing NWs lengths. In the meantime, larger Reset energy is required with a larger length for the same aspect‐ratio devices. Finally, the design range of the high aspect‐ratio is optimized in which the NWs length size is below 1.5 um and the aspect‐ratio ranges from 8:1 to 10:1. This work can provide guidance for the design of high‐aspect‐ratio 3D PCM with better MLC.