Characterization of the slow-state traps in 4H–SiC P-type MOS capacitor by a preconditioning technique with high positive voltage stress

Slow-state traps, including deep-level interface traps and near interface oxide traps, can degrade the mobility and reliability of 4H–SiC MOSFETs by carrier trapping and Coulomb scattering, hence the necessity to accurately evaluate them. In this letter, slow-state traps in the 4H–SiC P-CAP are characterized by a simple C–V measurement accompanied by a preconditioning with high voltage stress. The feasibility of this technique is verified by comparing it with both traditional bidirectional C–V and photo-CV measurements, and experimental results reveal that the stress preconditioning allows for an accurate extraction of slow-state trap density with high flexibility. The influence of stress time and stress voltage is investigated, and the properties of the detected slow-state traps are discussed via studying the emission process.