A High Throughput Fully Parallel FFT with CSD Constant Multiplier

This paper presents a fully parallel FFT architecture. In order to build hardware-efficient rotators, constant twiddle factors are converted into Canonical Signed Digit (CSD) representation to facilitate the implementation of rotators as shift-and-add operations. In addition, the word length of input and twiddle factors are reduced to meet the accuracy requirement, which further reduces the resource overhead and improves throughput. Experimental results show that the maximum clock frequency of the proposed 128-point fully parallel FFT architecture is close to 650MHz, and the throughput is up to 83GS/s.