TCAD Study on Suppression of Substrate-Induced Degradation in GaN-on-Si Integrated Half-Bridge Circuit by Local Si Lateral Etch

In this work, a high-voltage GaN-on-Si power integration platform is proposed, and a monolithically integrated half-bridge circuit is investigated by TCAD numerical simulations. The proposed platform exploits a local Si lateral etch from below the source contact of low-side transistor (LS-transistor). On a conventional GaN-on-Si platform, if the substrate is connected to the source of the LS-transistor, the high-side transistor (HS-transistor) suffers a negative back-gating effect that boosts up ${R}_{ \mathrm{\scriptscriptstyle ON}}$ ; if the substrate is connected to the source of HS-transistor, the LS-transistor suffers significant buffer trapping owing to the positive back-gating effect. On the proposed platform, the substrate is connected to source contact of HS-transistor. The positive back-gating effect to the LS-transistor is effectively suppressed by the local Si lateral etch. With a lateral etch of $12~\mu \text{m}$ extending beyond the source contact of LS-transistor, the dynamic $\vert {V}_{ \mathrm{\scriptscriptstyle ON}}\vert $ of the device is reduced from 1.89 to 1.09 V, approaching that of a discrete GaN transistor with substrate-to-source connection (1.02 V). Therefore, the proposed platform provides an effective approach toward high-voltage GaN power integrated circuits.