Influence of the source/drain doping region on the reconfigurability of ^BESOI MOSFET

This paper studies experimentally the influence of the N+ doped source/drain regions on the back enhanced with separate contacts SOI MOSFET ((SOI)-S-BE SC MOSFET) reconfigurability. The reconfigurable FET (RFET) proposed in this paper resulted in a drain current level in the same order of magnitude for both types of configurations (nMOS and pMOS). These results present a significant balanced drain current compared with the others (SOI)-S-BE device fabrications versions. In (SOI)-S-BE SC MOSFET, with programming gate voltage of vertical bar V-GB vertical bar=30V and drain voltage vertical bar V-D vertical bar=0.1V, the BESOI drain current reaches a value of, approximately, -1.4 mu A and 1.6 mu A, working as pMOS and nMOS respectively, which can be considered very well balanced.