Gradient Descent Iterative Correction Unit for Fixed Point Parity Based Codes

This paper proposes a novel iterative decoding method - Gradient Descent Symbol Update - for real number parity based error correction codes, as well as its corresponding hardware architecture. The decoding process is based on the gradient descent optimization technique, as well as binary maximum likelihood error correction decoding. We present the error correction performance and the convergence rate of the gradient descent symbol update for a parity based BCH (26,16) code. Furthermore, FPGA implementation results for the corresponding decoder architecture are depicted.