A 28nm 6GHz 2b Continuous-Time $\Delta\Sigma$ ADC with −101 dBc THD and 120MHz Bandwidth Using Digital DAC Error Correction

2022 IEEE International Solid-State Circuits Conference (ISSCC)(2022)

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摘要
Ultra-highly linear ADCs, based on continuous-time $\Delta\Sigma$ modulators with a (theoretically) linear 1b DAC, have demonstrated better than −100dBc THD in a bandwidth range from tens of kHz for audio to tens of MHz for broadband AM/FM radio [1]. To achieve both a large bandwidth and high dynamic range with a 1 b $\Delta\Sigma$ modulator, a high OSR and multi-GHz-rate sampling frequency are required. But there is a limit to the maximum sampling frequency of a $\Delta\Sigma$ modulator, being a negative feedback system, in order to maintain loop stability and sufficiently low metastability, for a given technology node. To date, the maximum achievable bandwidth of a high-resolution 1 b $\Delta\Sigma$ modulator is limited to a few tens of MHz. To achieve a bandwidth exceeding 100MHz with a single-loop $\Delta\Sigma$ modulator, multi-bit quantization is essential [3]–[5]. When employing multi-bit quantization, the inherently linear property of a 1b DAC that consists of only a single unit element is lost, due to processing imperfections that cause mismatch errors between the multiple unit elements of a multi-bit DAC. The impact of static and dynamic mismatch errors can be effectively reduced with calibration, dynamic matching and analog/digital compensation techniques. State-of-the-art ADCs with bandwidths exceeding 100MHz have reported excellent linearity numbers up to −83dBc THD [4]–[5], but this is far off from the <-100dBc THD achieved by the ultra-highly linear 1b ADCs. This paper demonstrates a 28nm CT $\Delta\Sigma$ ADC that achieves −101 dBc THD in a 120MHz bandwidth, exceeding the state-of-the-art by 17.5dB and 4.8 times, respectively [2]–[5]. The 120MHz bandwidth is realized by employing an offset-calibrated 2b quantizer sampled at 6GHz, and the linearity performance is achieved with a high precision, digitally corrected 2b DAC and has been validated over PVT and local mismatch variation.
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关键词
digital DAC error correction,ultra-highly linear ADCs,continuous-time ΛΣ modulators,linear 1b DAC,bandwidth range,high dynamic range,maximum sampling frequency,single-loop ΛΣ modulator,multibit quantization,single unit element,multibit DAC,static mismatch errors,dynamic mismatch errors,dynamic matching,state-of-the-art ADCs,excellent linearity numbers,ultra-highly linear 1b ADCs,linearity performance,CT ΛΣ ADC,continuous-time ΛΣ ADC,size 28.0 nm,frequency 6.0 GHz,bandwidth 100.0 MHz,bandwidth 120.0 MHz,word length 2 bit
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