Performance Analysis and Design of Hetero-Dielectric Heterojunction JLTFET with Impact of Interface Traps for Analogue/RF Applications

In this work reliability analysis of novel hetero-dielectric (HD) heterojunction JLTFET has been carried out. This has been performed through in-depth analysis of impact of trap charges existing at silicon oxide juncture on HD heterojunction JLTFET. Several dc performance attributes such as carrier concentration, electric field and analogue/RF performance attributes such as input characteristics, cut off frequency, TFP etc. has been studied. At the same time, comparison of results has been done with conventional heterojunction JLTFET. The proposed novel HD heterojunction JLTFET has been obtained through application of $\mathrm{H}\mathrm{f}\mathrm{O}_{2}$ oxide pocket at the drain side and source side in heterojunction JLTFET, resulting in enhanced device performance attributes. Apart from that, the results obtained depict that proposed novel HD heterojunction JLTFET is more immune to trap charges, and hence more reliable in comparison to conventional heterojunction JLTFET.