Enhancing fault tolerance in QCA-based RAM cells: A USE clock-driven approach with a novel majority voter

CMOS IC technology is encountering limitations due to fabrication challenges, matching characteristics, and the pursuit of miniaturization. These constraints have prompted the exploration of alternative technologies to cater to the demands of the nanoscale realm. Quantum Dot Cellular Automata (QCA) has emerged as a promising candidate for implementing digital systems at the nanoscale. However, given the nascent stage of QCA technology, the risk of defects during fabrication in the nano-regime is a significant concern. Consequently, the development of fault-tolerant circuits and systems becomes pivotal for the practical realization of this technology. In this study, we introduce a fault-tolerant 3-input majority voter (FT-MV3) designed to achieve 100% fault tolerance against single-cell omission and additional-cell defects. We also assess the fault tolerance of this design in the presence of other fabrication defects. Furthermore, our study includes an energy dissipation analysis of the proposed design. Additionally, we present layout designs for fault-tolerant RAM cells, both with and without the Universal, Scalable, and Efficient (USE) clocking scheme. Our findings demonstrate that the USE-based RAM cell design exhibits an impressive fault tolerance of 95.52% against single-cell omission defects, making it a robust choice for the implementation of reliable RAM architectures.