Comprehensive Design Methodology of Dopant Profile to Suppress Gate-LER-induced Threshold Voltage Variability in Sub-30 Nm NMOSFETs
IEICE Technical Report IEICE Tech Rep(2009)
AI 理解论文
溯源树
样例
生成溯源树,研究论文发展脉络
Chat Paper
正在生成论文摘要
IEICE Technical Report IEICE Tech Rep(2009)