Exploring Dynamic Duty Cycling for Energy Efficiency in Coherent DSP ASIC

In coherent optics transmission systems, the Digital Signal Processor (DSP) Application-Specific Integrated Circuit (ASIC) is the most power hungry part of the optical transceiver. Already in the edge of transistor technology, to achieve the power budget, we must look for opportunities to further optimize the designs. This paper explores dynamic duty cycle for reducing the consumption in the pipeline of such DSP ASICs. We exploit the characteristics of estimator algorithms to introduce dynamic duty cycle, reducing the mean consumption of designs originally constrained only for worst-case scenarios. We present the methodology to implement duty cycle control using the Carrier Frequency Offset Estimator (CFE) algorithm as case study, achieving in simulation level from 22% to 74% power consumption reduction in this algorithm, varying on chip operation conditions.