Design of an E-TSPC Flip-Flop for a 43 Gb/s PRBS Generator in 22 nm FDSOI

This work presents the design of an extended true single-phase-clock (E-TSPC) flip-flop (FF) optimized for minimum clock-to-output delay in a 22nm fully-depleted silicon on insulator (FDSOI) technology. The FFs are used to form a pseudo-random binary sequence (PRBS) generator, which achieves a maximum bit rate of 43 Gb/s at a power consumption of 2.63mW. This marks a bit rate increase of 30% compared to its TSPC-based counterpart. The circuit, which occupies a core area of only 34 mu m(2), achieves an excellent FoM of 5.56 (fJ)/(Bit) comparable to the best reported in the literature. To the authors' knowledge, the reached bit rate marks the highest value reported in the literature for TSPC or E-TSPC PRBS generators.