A Power-Efficient 10T D Flip-Flop with Dual Line of Four Switches using 65nm CMOS Technology

D flip-flops play a critical role as components in digital circuits, providing the ability to store data and ensure synchronization. In the realm of AI and modern digital electronics, the increasing need for low power consumption, high-speed operation, and miniaturization stems from the desire to enhance energy efficiency, enable real-time processing, and seamlessly integrate AI functionalities into compact and portable devices. These technological advancements will significantly contribute to the widespread adoption of AI across various industries and applications. We propose a novel 10T D Flip-Flop structure with NMOS switch-based pass gate and Inverter. The proposed circuit is designed and simulated at 1.2 V in a 65-nm CMOS process and uses the fewest transistors, compared to other conventional D flip-flop circuits, and the average power consumption is approximately 29 times lower than the most recently proposed TSPC flip-flop circuit.