A 10-Gb/s Dual-Loop Reference-less CDR with FD Controller

A 10-Gb/s dual-loop reference-less clock data recovery (CDR) circuit with a FD controller is proposed for serial interface applications. The proposed FD controller disables the FD loop to improve the jitter characteristics in normal operation mode after the CDR is locked in training mode. The proposed reference-less CDR is implemented using a 65nm 1 poly 9-metal CMOS process with a supply of 1.2 V. Its area containing the FD controller is 640 mu m x 480 mu m. Its power consumption is 70 mW in training mode and 55mW in operation mode. For input data encoded in 8b10b with a data rate of 10 Gb/s, a clock with a frequency of 5 GHz recovered by the proposed dual-loop reference-less CDR has a peak-to-peak time jitter of less than 2 ps.