Thermal Finite Element Simulation of Ultrafine Pitch Chip-to-Wafer Hybrid Bonding

Cu/SiO 2 hybrid bonding is a promising solution for three-dimensional(3D) integration because it can achieve ultrafine pitch interconnection. This paper design and simulate the expansion and shrinkage of Cu caused by temperature change during annealing by finite element analysis. The effect of pad shape/size/depth, initial dishing depth, and annealing temperature of Cu pad on the expansion deformation are studied in detail. In addition to the deformation, emphasis is placed on the peeling stress, which includes SiO 2 interface peeling caused by the Cu expansion in the heating stage and Cu interface peeling caused by the Cu shrinkage in the cooling stage. These two peeling stresses bring the risk of interfacial de-bonding respectively. Especially, the pad arrangement arrays of triangular, square and hexagon are designed to study the difference of overall interface stress distribution.