Establishment of Analytical Model for the Gate to Source Capacitance of Power MOSFET

In the actual HBM test, it is found that the ESD test results of various power MOSFET devices show asymmetry between forward and reverse withstand voltages, while the ESD process does not distinguish between positive and negative directions. Large differences in forward and reverse withstand voltages are unacceptable for power MOSFETs or as ESD protection devices. The problem of its causing device failure is particularly pronounced. In this paper, by establishing the analytical model of gate to source capacitance of SGT-MOSFET, VUMOSFET and VDMOS under the forward and reverse voltages, we comparatively analyze the reasons for the asymmetry of the forward and reverse withstand voltages and their different ratios of the three kinds of power MOSFET, which provides a theoretical basis for the testing of the device's ESD and the analysis of its reliability. It is found that the ESD forward and reverse withstand voltage asymmetry phenomenon of different power MOSFET structures is related to the variation of gate to source capacitance caused by the reverse-type layer. When a forward voltage is applied between the gate and source, the device gate to source capacitance consists of the oxide layer capacitance around the gate in parallel; when a reverse voltage is applied, the gate to source capacitance consists of the virtual gate to drain capacitance in series with the inverse layer capacitance and then in parallel with the other oxide layer capacitance around the gate. This results in a decrease in the gate to source capacitance at the reverse voltage, making the device reverse withstand voltage greater than the forward withstand voltage. The difference in the ratio of ESD reverse withstand voltage to forward withstand voltage for different devices is related to the change in the capacitance of the inverse layer in the gate to source capacitor under reverse voltage caused by the difference in device structure.