A 0.35mm 94.25μ W Fully Integrated NFC Tag IC Using 0.13μ m CMOS Process.
IEEE Trans. Circuits Syst. I Regul. Pap.(2024)
摘要
An NFC tag chip employing the ISO/IEC14443-A protocol is developed in SMIC 0.13
$\upmu$
m EEPROM 2P6M CMOS process, boasting a chip area of 620.03
$\upmu$
m
$\times$
567.93
$\upmu$
m and a power consumption of under 100
$\upmu$
W. The chip addresses critical issues such as reducing power consumption and minimizing area costs for covering numerous IoT nodes. For a small area of the chip, a specialized ESD protection circuit is proposed, efficiently multiplexing discharge transistors, cross-gate connected rectifiers, limiters for overvoltage protection, and load switch modulators within the chip’s limited space. For power efficiency, a compact 175.44
$\upmu$
m
$\times$
32.98
$\upmu$
m 18.52
$\upmu$
A LDO based on the current mirror and current feedback is presented for the DC supply during the 100% ASK modulation. Additionally, an ASK demodulator and a 13.56MHz
$\pm$
kHz clock generator are designed in compact areas of 62.19
$\upmu$
m
$\times$
56.06
$\upmu$
m and 24.76
$\upmu$
m
$\times$
13.14
$\upmu$
m, respectively. These components ensure stable protocol communication with digital circuits and support a 7kb EEPROM, providing a comprehensive solution for NFC-based IoT information collection.
更多查看译文
关键词
ISO/IEC14443-A,NFC tag,low area cost,low power consumption,ASK demodulation
AI 理解论文
溯源树
样例
生成溯源树,研究论文发展脉络
Chat Paper
正在生成论文摘要