A 0.078 pJ/SOP Unstructured Sparsity-Aware Spiking Attention/Convolution Processor with 3D Compute Array.
IEEE Custom Integrated Circuits Conference（2024）
Key words
Time Step,Transformer,Energy Efficiency,Power Consumption,Parallelization,Maximum Efficiency,ImageNet,Critical Challenge,Task Accuracy,Load Balancing,Partial Sums,Gesture Recognition,Sparsity Level,Search Window,Space Consumption,Advanced Architectures,3D Array,High Sparsity,Input Spike,Multiple Time Steps
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