A Reduced-Order Digital Twin FPGA-Based Implementation with Self-Awareness Capabilities for Power Electronics Applications
IEEE Journal of Radio Frequency Identification（2024）
Key words
Digital twins,Buck converters,Field programmable gate arrays,Read only memory,Cloud computing,Real-time systems,Computational modeling,Digital twin,flyback converter,smart control engineering,FPGA,embedded digital twin,Industry 4.0
AI Read Science
Must-Reading Tree
Example
Generate MRT to find the research sequence of this paper
Chat Paper
Summary is being generated by the instructions you defined