A 112-Gb/s PAM-4 Retimer Transceiver with Jitter-Filtering Clocking Scheme and BER Optimization Technique in 28-Nm CMOS
IEEE Journal of Solid-State Circuits（2025）
Key words
Analog-to-digital converter (ADC),bit-error-rate (BER) optimization,continuous-time linear equalizer (CTLE),digital signal processing (DSP),four-level pulse amplitude modulation (PAM-4),retimer,wireline transceiver
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