On-Chip Implementation of Cascaded Integrated Comb filters (CIC) for DSP Application
On-Chip Implementation of Cascaded Integrated Comb filters (CIC) for DSP Application
Research Student Seminar SPS05. Faculty of Engineering, National University of Malaysia , pp. 97-102
This paper presents the design of a CIC filters based on a low-pass filter for reducing the sampling rate, also known as decimation process. The targeted application for the filter is in the analog to digital conversion (ADC).The CIC is chosen because of its attractive property of both low power and complexity since it dose not required multipliers. Simulink toolbox available in Matlab software is used to design and simulate the functionality of the CIC filter. This paper also shows how sample frequency is decreased by CIC filter and it can be used to give enough stop-band attenuation to prevent aliasing after decimation.
An Enhancement of Decimation Process using Fast Cascaded Integrator Comb (CIC) Filter
An Enhancement of Decimation Process using Fast Cascaded Integrator Comb (CIC) Filter
IEEE International Conference on Semiconductor Electronics. Malaysia, pp. 811-815, DOI: 10.1109/SMELEC.2006.380749
The over sampling technique has been shown to increase the SNR and is used in many high performance system such as in the ADC for audio and DAT systems. This paper presents the design of the decimation and its VLSI implementation which is the sub-component in the over sampling technique. The design of three main units in the decimation stage that is the Cascaded Integrator Comb (CIC) filter, the associated half band filters and the droop correction are also described. The Verilog HDL code in Xilinx ISE environment has been derived to describe the CIC filter properties and downloaded in to Virtex II FPGA board. In the design of these units, we focus on the trade-off between the speed improvement and the power consumption as well as the silicon area for the chip implementation.
VLSI Implementation of Cascaded Integrator Comb Filters for DSP Applications
VLSI Implementation of Cascaded Integrator Comb Filters for DSP Applications
4th National Technical Postgraduate Symposium, TechPos 2006. Faculty of Engineering, University of Malaya, Malaysia, pp. 54-58
The recursive comb filters or Cascaded Integrator Comb filter (CIC) are commonly used as decimators for the sigma delta modulators. This paper presents the VLSI implementation, analysis and design of high speed CIC filters which are based on a low-pass filter. These filters are used in the signal decimation which has the effect on reducing the sampling rate. It is also chosen because its attractive property of both low power and low complexity since it dose not required a multiplier. Simulink toolbox available in Matlab software which is used to simulator and Verilog HDL coding help to verify the functionality of the CIC filters. Design procedures and examples are given for CIC filter with emphasis on frequency response, transfer function and register width. The implementation results show using Modified Carry Look-ahead Adder for summation and also apply pipelined filter structure enhanced high speed and make it more compatible for DSP applications.
An Improved Recursive and Non-recursive Comb Filter for DSP Applications
An Improved Recursive and Non-recursive Comb Filter for DSP Applications
The 6th Asian Control Conference. Institute Technology Bandung & IEEE Indonesia, 413-417
The recursive and non-recursive comb filters are commonly used as decimators for the sigma delta modulators. This paper presents the analysis and design of low power and high speed comb filters. The comparison is made between the recursive and the non-recursive comb filters with the focus on high speed and saving power consumption. Design procedures and examples are given by using Matlab and Verilog HDL for both recursive and non-recursive comb filter with emphasis on frequency response, transfer function and register width. The implementation results show that non-recursive comb filter has capability of speeding up the circuit and reducing power compared to recursive one when the decimation ratio and filter order are high. Using Modified Carry Look-ahead Adder for summation and also apply pipelined filter structure makes it more compatible for DSP application.
An Overview of the Decimation process and its VLSI implementation
An Overview of the Decimation process and its VLSI implementation
Research Student Seminar SPS06. Faculty of Engineering, National University of Malaysia , pp. 207-211
On-Chip Implementation of High Speed and High resolution Pipeline Radix 2 FFT Algorithm
On-Chip Implementation of High Speed and High resolution Pipeline Radix 2 FFT Algorithm
International Conference on Intelligent and Advanced System ICIAS 2007 organized by IEEE. University Technology Petronas, Malaysia. ISBN: 978-1-4244-1355-3 pp. 1286 – 1288
A new on-chip implementation of Fast Fourier Transform (FFT) based on Radix 2 is presented. The pipeline and parallel approaches are combined to introduce a new high speed FFT algorithm which increases resolution by using floating point calculations in its structures. The design has the merits of low complexity and high speed performance. Furthermore, latency reduction is an important issue to implement the high speed FFT on FPGA. The proposed FFT algorithm shows the latency of (N/2 log(2) N) + 11. Moreover, this algorithm has the advantage of low mean squared error (MSE) of 0.0001 which is preferable to Radix 2 FFT.
VLSI implementation of high speed and high resolution FFT algorithm based on radix 2 for DSP application
5th IEEE Student Conference on Research and Development, SCOReD 2007. National University of Malaysia, ISBN: 978-1-4244-1470-3, pp.1-4
Using Fast Fourier Transform (FFT) is indispensable in most signal processing applications. Designing an appropriate algorithm for the implementation of FFT can be efficacious in digital signal processing. Sophisticated techniques such as pipelining and parallel calculations have potential impacts on VLSI implementation of FFT algorithm. Furthermore, a mathematic approach such as floating point calculation achieves higher precision. In this paper, an efficient algorithm with using parallel and pipelining methods is proposed to implement high speed and high resolution FFT algorithm. Latency reduction is an important issue to implement the high speed FFT on FPGA. The Proposed FFT algorithm shows the latency of 5131 clock pulse when N refers to 1024 points. The design has the mean squared error (MSE) of 0.0001 which is preferable to Radix 2 FFT.
VLSI Implementation of High Resolution High Speed Low Latency Pipeline Floating point Adder/Subtractor for FFT Applications
International Conference on NanoTech. pp: 327-331. ISSN: 9789834 492106
Design of automatic soil humidity control using Maximum Power Point Tracking controller
Design of automatic soil humidity control using Maximum Power Point Tracking controller
IEEE Student Conference on Research and Development, SCOReD 2010. pp: 1-5. DOI: 978-14244-8648-9/10
The effect of the digit slicing architecture on the FFT butterfly
The effect of the digit slicing architecture on the FFT butterfly
IEEE International Conference on Information Science Signal Processing and their Application. ISSPA 2010. Malaysia. pp. 802-805
Most communications systems tend to achieve bandwidth, power and cost efficiencies to capable to describe modulation scheme. Hence for signal modulation orthogonal frequency division multiplexing (OFDM) transceiver is introduced to cover communications demand in four generation. However high performance Fast Fourier Transforms (FFT) as a main heart of OFDM acts beyond the view. In order to achieve capable FFT, design and realization of its efficient internal structure is key issues of this research work. In this paper implementation of high performance butterfly for FFT by applying digit slicing technique is presented. The proposed design focused on the trade-off between the speed and active silicon area for the chip implementation. The new architecture was investigated and simulated with the MATLAB software. The Verilog HDL code in Xilinx ISE environment was derived to describe the FFT Butterfly functionality and was downloaded to Virtex II FPGA board.
FPGA Implementation of Pipeline Digit-Slicing Multiplier-Less Radix 22 DIF SDF Butterfly for Fast Fourier Transform Structure
The 5th European Conference on Antennas and Propagation (EUCAP2011). Pp 4168- 4172
The need for wireless communication has driven the communication systems to high performance. However, the main bottleneck that affects the communication capability is the Fast Fourier Transform (FFT), which is the core of most modulators. This paper presents FPGA implementation of pipeline digit-slicing multiplier-less radix 22 DIF (Decimation In Frequency) SDF (single path delay feedback) butterfly for FFT structure. The approach taken; in order to reduce computation complexity in butterfly multiplier, digit-slicing multiplier-less technique was utilized in the critical path of pipeline Radix-22 DIF SDF FFT structure. The proposed design focused on the trade-off between the speed and active silicon area for the chip implementation. The multiplier input data was sliced into four blocks each one with four bits to process at the same time in parallel. The new architecture was investigated and simulated with MATLAB software. The Verilog HDL code in Xilinx ISE environment was derived to describe the FFT Butterfly functionality and was downloaded to Virtex II FPGA board. Consequently, the Virtex-II FG456 Proto board was used to implement and test the design on the real hardware. As a result, from the findings, the synthesis report indicates the maximum clock frequency of 555.75 MHz with the total equivalent gate count of 32,146 is a marked and significant improvement over Radix 22 DIF SDF FFT butterfly. In comparison with the conventional butterfly architecture design which can only run at a maximum clock frequency of 200.102 MHz and the conventional multiplier can only run at a maximum clock frequency of 221.140 MHz, the proposed system exhibits better results. It can be concluded that on-chip implementation of pipeline digit-slicing multiplier-less butterfly for FFT structure is an enabler in solving problems that affect communications capability in FFT and possesses huge potentials for future related works and research areas.
Optimised toolbox for the design of rotary reluctance motors
Optimised toolbox for the design of rotary reluctance motors
2011 IEEE Conference on Sustainable Utilization and Development in Engineering and Technology. pp 1-6. DOI: 10.1109/STUDENT.2011.6089318
Operation of the rotary reluctance machine is highly affected due to the sequential attraction-repulsion principle of the adjacent phase excitation. The problem has been identified and addressed by various researchers in the past decades. Effective magnetic design is one way of minimizing the effect. However it is tedious and time consuming as the design procedure involve higher analytical derivation and calculations. This paper presents a simpler graphical user interface toolbox to use for the design of reluctance motors. The developed interface calculates the analytical values of the aligned, unaligned and intermediate inductance values so that the user can interpret the inductance and torque profile easily. A new analytical method called Cyclic Integration Method (CIM) is proposed and is used for the performance evaluation of the designed tool box.
Universal Computer aided design for electrical machines
Universal computer aided design for electrical machines
IEEE 8th International colloquium on signal Processing Applications conference (CSPA 2012). pp: 99-104. DOI: 10.1109/CSPA.2012.6194699
Electrical machines are devices that change either mechanical or electrical energy to the other and also can alternate the voltage levels of an alternating current. The need for electrical machines cannot be overemphasized since they are used in various applications in the world today. Its design is to meet the specifications as stated by the user and this design has to be an economical one. The design therefore revolves around designing the machine to meet the stipulated performance required, the cost available and the lasting life of the machine. This work aims to eliminate the tediousness involved in the manual hand calculations of designing the machines by making use of a graphical user interface and using iterations in situations where the data would have been assumed.
On-Chip Implementation of Pipeline Digit-Slicing Multiplier-Less Butterfly for Fast Fourier Transform Architecture
American Journal of Engineering and Applied Sciences. 3(4):757-764. ISSN 1941-7020 DOI: 10.3844/ajeassp.2010.757.764.
The need for wireless communication has driven the communication systems to high performance. However, the main bottleneck that affects the communication capability is the Fast Fourier Transform (FFT), which is the core of most modulators. This study presents on-chip implementation of pipeline digit-slicing multiplier-less butterfly for FFT structure. The approach taken; in order to reduce computation complexity in butterfly, digit-slicing multiplier-less single constant technique was utilized in the critical path of Radix-2 Decimation In Time (DIT) FFT structure. The proposed design focused on the trade-off between the speed and active silicon area for the chip implementation. The new architecture was investigated and simulated with MATLAB software. The Verilog HDL code in Xilinx ISE environment was derived to describe the FFT Butterfly functionality and was downloaded to Virtex II FPGA board. Consequently, the Virtex-II FG456 Proto board was used to implement and test the design on the real hardware. As a result, from the findings, the synthesis report indicates the maximum clock frequency of 549.75 MHz with the total equivalent gate count of 31,159 is a marked and significant improvement over Radix 2 FFT butterfly. In comparison with the conventional butterfly architecture, design that can only run at a maximum clock frequency of 198.987 MHz and the conventional multiplier can only run at a maximum clock frequency of 220.160 MHz, the proposed system exhibits better results. The resulting maximum clock frequency increases by about 276.28% for the FFT butterfly and about 277.06% for the multiplier. It can be concluded that on-chip implementation of pipeline digit-slicing multiplier-less butterfly for FFT structure is an enabler in solving problems that affect communications capability in FFT and possesses huge potentials for future related works and research areas.
On-Chip Implementation of High Resolution High Speed Floating Point Adder/Subtractor with Reducing Mean Latency for OFDM
American Journal of Engineering and Applied Sciences. 3(1): 25-30. ISSN: 1941-7020. DOI: 10.3844/ajeassp.2010.25.30
Fast Fourier transform (FFT) is widely applied in OFDM trance-receiver communications system. Hence Efficient FFT algorithm is always considered. This paper proposed FPGA realization of high resolution high speed low latency floating point adder/subtractor for FFT in OFDM trance-receiver. The design was implemented for 32 bit pipelined adder/subtractor which satisfied IEEE-754 Standard for floating-point Arithmetic. The design was focused on the trade-off between the latency and speed improvement as well as resolution and silicon area for the chip implementation. In order to reduce the critical path and decrease the latency, the novel structure was designed and investigated. Consequently, synthesis report indicated the latency of 4 clock cycles due to each stage operated within just one clock cycle. The unique structure of designed adder well thought out resulted 6691 equivalent gate count and lead us to obtain low area on chip. The synthesis Xilinx ISE software provided results representing the estimated area and delay for design when it is pipelined to various depths. The report shows the minimum delay of 3.592 ns or maximum frequency of 278.42 MHz
VLSI Implementation of Novel Class of High Speed Pipelined Digital Signal Processing Filter for Wireless Receivers
American Journal of Engineering and Applied Sciences. 3(4):663-669. ISSN 1941-7020. DOI:10.3844/ajeassp.2010.663.669
The need for high performance transceiver with high Signal to Noise Ratio (SNR) has driven the communication system to utilize latest technique identified as over sampling systems. It was the most economical modulator and decimation in communication system. It has been proven to increase the SNR and is used in many high performance systems such as in the Analog to Digital Converter (ADC) for wireless transceiver. This research work presented the design of the novel class of decimation and its VLSI implementation which was the sub-component in the over sampling technique. The design and realization of main unit of decimation stage that was the Cascaded Integrator Comb (CIC) filter, the associated half band filters and the droop correction are also designed. The Verilog HDL code in Xilinx ISE environment has been derived to describe the proposed advanced CIC filter properties. Consequently, Virtex-II FPGA board was used to implement and test the design on the real hardware. The ASIC design implementation was performed accordingly and resulted power and area measurement on chip core layout. The proposed design focused on the trade-off between the high speed and the low power consumption as well as the silicon area and high resolution for the chip implementation which satisfies wireless communication systems. The synthesis report illustrates the maximum clock frequency of 332 MHz with the active core area of 0.308×0.308 mm2. It can be concluded that VLSI implementation of proposed filter architecture is an enabler in solving problems that affect communication capability in DSP application.