Networks of mobile devices and embedded systems represent a new computing platform. Typical network nodes range from sensors, cell phones, PDA's, to laptop computers. Wireless ad-hoc networks are used to connect these heterogeneous nodes, each of which has different capabilities and resources and may provide different services. Most applications targeting such networks will exploit the physical locations of the network nodes. SpatialViews is a language for applications executing on volatile networks of mobile devices and embedded systems. SpatialViews provides high-level abstractions for dynamic service discovery, location-awareness, and in-network aggregation. The compiler translates a SpatialViews program into low-level representations that use light-weight execution migration and property based routing.This paper investigates the impact of parallelization and replication on program performance metrics such as response time, energy consumption, and quality of result (QoR). For a simple application program running over networks with a range of different node failure rates, analytical modeling, simulation, and physical measurement revealed different energy/response time/QoR tradeoffs among different parallelization strategies and replication degrees.
Charm++, a parallel object language based on the idea of virtual processors, has attained significant success in efficient parallelization of applications. Requiring the user to only decompose the computation into a large number of objects ("virtual processors"), Charm++ empowers its intelligent adaptive runtime system to assign and reassign the objects to processors at runtime. This facility is used to optimize execution, including dynamic load balancing. However, in complex applications, Charm++ programs obscure the overall flow of control: one must look at the code of multiple objects to discern how the sets of objects are orchestrated in a given application. In this paper, we present an orchestration notation that allows expression of Charm++ functionality without its fragmented flow of control.
Trust asymmetry is a core, albeit rarely discussed, problem in scalable computing. Techniques for protecting a host's operating system (and other processes) from a user's process are well understood and widely deployed. However, there is currently no way to protect the user's process from the OS. Hence, while the host's owner need not trust the user at all, the user must trust the owner completely. This, we argue, leads to practical limits to scalability for computation that, because of encryption, simply do not exist for communication. We argue that it is imperative for the grid computing community to address this problem using encrypted computation techniques. We then propose a simple mechanism for encrypted computation of Boolean circuits and show how it can likely be generalized for use in an object code translator.
Virtual machine grid computing greatly simplifies the use of widespread computing resources by lowering the level of abstraction, benefiting both resource providers and users. For the user, the Virtuoso middleware that we are developing closely emulates the existing process of buying, configuring and using machines. VNET, a component of Virtuoso, is a simple and efficient layer two virtual network tool that makes these virtual machines appear to be connected to the home network of the user, simplifying network management. Overlays like VNET have great potential as the mechanism for adaptation. Here, we describe our second generation VNET implementation, which includes support for arbitrary topologies and routing, application topology inference, and adaptive control of the overlay. We demonstrate that the performance of unmodified applications, in particular bulk synchronous parallel applications running inside the virtual machines and serviced by VNET, can be significantly (up to a factor of two) enhanced by adapting the VNET topology and forwarding rules on the fly based on intelligent application traffic inference methods. The adaptation scheme requires no knowledge or participation from the user or application developer.
Peer-to-peer systems have grown significantly in popularity over the last few years. An increasing number of research projects have been closely following this trend, looking at many of the paradigm's technical aspects. In the context of data-sharing services, efforts have focused on a variety of issues from object location and routing to fair sharing and peer lifespans. Overall, the majority of these projects have concentrated on either the whole P2P infrastructure or the client-side of peers. Little attention has been given to the peer's server-side, even when that side determines much of the everyday-user's experience. In this paper, we make the case for looking at the server-side of peers, focusing on the problem of scheduling download requests at the server-side of P2P systems with the intent of minimizing the average response time experienced by users. We start by characterizing server workload based on extensive trace collection and analysis. We then evaluate the performance and fairness of different scheduling policies through trace-driven simulations. Our results show that average response time can be dramatically reduced by more effectively scheduling the requests on the server-side of P2P systems.
Splay trees, a type of self-adjusting search tree, are introduced and analyzed. Since they have been widely used in search problems, any performance improvements will yield great benefits. First, the paper introduces some background about splay trees and memory hierarchies. Then, it presents two heuristic algorithms, based on research in reference affinity and data regrouping. These algorithms have good locality, reduce memory transfers, and decrease cache miss rates on different architectures. Finally, the paper evaluates the performance gain of these algorithms on random inputs and Spec2K benchmark programs.
This paper explores the potential for automatic cross-component optimisation in the Python / VTK-based MayaVi modular visualisation environment. The idea is to delay execution of the VTK components called from the MayaVi tool, which requires no significant structural change to the MayaVi code base, but which opens up the possibility for dynamic performance optimisations such as tiling, fusion, memoisation and shared-memory parallelisation. The paper concludes with experimental results on an unstructured mesh hierarchy model from an adaptive three-dimensional gravity current simulation.
Knowledge of data values at run-time allows us to generate better code in terms of efficiency, size and power consumption.This paper introduces a low-level compiling technique based on a minimal code generator with parametric embedded sections to generate binary code at run-time. This generator called a "compilet" creates code and allocates registers using the data input. Then, it generates the needed instructions. Our measurements, performed on Itanium 2 and PowerPC platforms have shown a speed improvement of 43% on the Itanium 2 platform and 41% on the PowerPC one.The proposed technique proves to be particularly useful in the case of intensively reused functions in graphic applications, where the advantages of dynamic compilation have not been fully taken into account yet.
Scientific applications contain program sections that exhibit repetitive data accesses. This paper proposes combined compile-time/runtime data reference analysis techniques that exploit repetitive data access behavior in both regular and irregular program sections. We present a new compiler algorithm to detect such repetitive data references and an API to an underlying software distributed shared memory (software DSM) system to orchestrate the learning and pro-active reuse of communication patterns. We evaluate the combined compile-time/runtime system on a selection of OpenMP applications, exhibiting both regular and irregular data reference patterns, resulting in average performance improvement of 28.1% on 8 processors.
This paper presents runtime mechanisms that enable flexible use of speculative precomputation in conjunction with thread-level parallelism on SMT processors. The mechanisms were implemented and evaluated on a real multi-SMT system. So far, speculative precomputation and thread-level parallelism have been used disjunctively on SMT processors and no attempts have been made to compare and possibly combine these techniques for further optimization. We present runtime support mechanisms for coordinating precomputation with its sibling computation, so that precomputation is regulated to avoid cache pollution and sufficient runahead distance is allowed from the targeted computation. We also present a task queue mechanism to orchestrate precomputation and thread-level parallelism, so that they can be used conjunctively in the same program. The mechanisms are motivated by the observation that different parts of a program may benefit from different modes of multithreaded execution. Furthermore, idle periods during TLP execution or sequential sections can be used for precomputation and vice versa. We apply the mechanisms in loop-structured scientific codes. We present experimental results that verify that no single technique (precomputation or TLP) in isolation achieves the best performance in all cases. Efficient combination of precomputation and TLP is most often the best solution.
This paper introduces a method to monitor an application and generate a short synthetic "memory skeleton" program whose memory access pattern is representative of the application. In particular, the application and its memory skeleton should have similar cache behavior on any memory hierarchy architecture. The objective is to quickly estimate the cache performance of an application on any memory architecture by running its memory skeleton. The paper presents and validates a framework for automatic construction of memory skeletons. The approach is based on sampling the address trace of an executing application, summarizing it, and then employing it to generate a synthetic memory skeleton program. The broad goal of this research is construction of "performance skeletons" designed to quickly estimate the performance of a large application in an unpredictable environment. A performance skeleton must also mimic the communication and execution behavior of the application. However, the memory behavior drives the performance of many scientific applications and hence memory skeletons are a critical component of this approach to performance estimation.
Software Transactional Memory (STM) is a generic non-blocking synchronization construct that enables automatic conversion of correct sequential objects into correct concurrent objects. Because it is nonblocking, STM avoids traditional performance and correctness problems due to thread failure, preemption, page faults, and priority inversion.In this paper we compare and analyze two recent object-based STM systems, the DSTM of Herlihy et al. and the FSTM of Fraser, both of which support dynamic transactions, in which the set of objects to be modified is not known in advance. We highlight aspects of these systems that lead to performance tradeoffs for various concurrent data structures. More specifically, we consider object ownership acquisition semantics, concurrent object referencing style, the overhead of ordering and bookkeeping, contention management versus helping semantics, and transaction validation. We demonstrate for each system simple benchmarks on which it outperforms the other by a significant margin. This in turn provides us with a preliminary characterization of the applications for which each system is best suited.
This paper compares the performance of Myrinet and Ethernet as a communication substrate for MPI libraries. MPI library implementations for Myrinet utilize user-level communication protocols to provide low latency and high bandwidth MPI messaging. In contrast, MPI library implementations for Ethernet utilize the operating system network protocol stack, leading to higher message latency and lower message bandwidth. However, on the NAS benchmarks, GM messaging over Myrinet only achieves 5% higher application performance than TCP messaging over Ethernet. Furthermore, efficient TCP messaging implmentations improve communication latency tolerance, which closes the performance gap between Myrinet and Ethernet to about 0.3% on the NAS benchmarks. This shows that commodity networking, if used efficiently, can be a viable alternative to specialized networking for high-performance message passing.
To minimize work lost due to system failures, large parallel applications perform periodic checkpoints. These checkpoints are typically inserted manually by application programmers, resulting in synchronous checkpoints, or checkpoints that occur at the same program point in all processes. While this solution is tenable for current systems, it will become problematic for future supercomputers that have many tens of thousands of nodes, because contention for both the network and file system will grow. This paper shows that staggered checkpoints---globally consistent checkpoints in which processes perform checkpoints at different points in the code---can significantly reduce network and file system contention. We describe a compiler-based approach for inserting staggered checkpoints, and we show, using trace-driven simulation, that staggered checkpointing is 23 times faster that synchronous checkpointing.
A lack of efficient system software is an increasing impediment to deploying large-scale parallel and distributed systems. Systemically addressing operating system-induced performance anomalies requires accurate, low-overhead, whole-system monitoring, something that is currently unavailable in large tightly-coupled systems. In this paper, we present the design of IMPuLSE---Integrated Monitoring and Profiling for Large-Scale Environments---a system we are developing to meet this need. IMPuLSE's innovative message-centric profiling approach trades off of centralized global knowledge for low overhead, while retaining relatively fine-grained information about important cross-host performance interactions. The goal of this approach is to enable both large-scale system software adaptation and continuous system performance auditing.
This paper defines the requirements for effective execution of iterative computations requiring communication on a desktop grid. It then proposes a combination of a p2p communication model, an algorithmic approach (asynchronous iterations) and a programming model which has promise for satisfying those requirements. Experimental results from an implementation of asynchronous algorithms in pure p2p system will be given. The integration of the p2p communication model with a commercially supported implementation of the SETI@Home desktop grid system to yield a prototype implementation of a desktop grid with communication among its hosts is described and some very preliminary results from application of the extended desktop grid for computation of Google pageranks and solution of linear systems are given. The desktop grid prototype preserves anonymity among desktop hosts, supports dynamic communication set membership and enables transparent replication of computations for fault tolerance.
Ad-hoc networks of mobile devices such as smart phones and PDAs represent a new and exciting distributed system architecture. Building distributed applications on such an architecture poses new design challenges in programming models, languages, compilers, and runtime systems. This paper discusses SpatialViews, a high-level language designed for programming mobile devices connected through a wireless ad-hoc network. SpatialViews allows specification of virtual networks with nodes providing desired services and residing in interesting spaces. These nodes are discovered dynamically with user-specified time constraints and quality of result (QoR). The programming model supports "best-effort" semantics, i.e., different executions of the same program may result in "correct" answers of different quality. It is the responsibility of the compiler and runtime system to produce a high-quality answer for the particular network and resource conditions encountered during program execution. Four applications, which exercise different features of the SpatialViews language, are presented to demonstrate the expressiveness of the language and the efficiency of the compiler generated code. The applications are an application that collects and aggregates sensor data in network, an application that performs dynamic service installation, a mobile camera application that supports computation offloading for image understanding, and an augmented-reality (AR) Pacman game. The efficiency of the compiler generated code is verified through simulation and physical measurements. The reported results show that SpatialViews is an expressive and effective language for ad-hoc networks. In addition, compiler optimizations can significantly improve response times and energy consumption.
In this paper, we show our initial experience with a class of objects, called Hierarchically Tiled Arrays (HTAs), that encapsulate parallelism. HTAs allow the construction of single-threaded parallel programs where a master process distributes tasks to be executed by a collection of servers holding the components (tiles) of the HTAs. The tiled and recursive nature of HTAs facilitates the adaptation of the programs that use them to varying machine configurations, and eases the mapping of data and tasks to parallel computers with a hierarchical organization. We have implemented HTAs as a MATLAB™ toolbox, overloading conventional operators and array functions such that HTA operations appear to the programmer as extensions of MATLAB™. Our experiments show that the resulting environment is ideal for the prototyping of parallel algorithms and greatly improves the ease of development of parallel programs while providing reasonable performance.
As an alternative to message passing, Rochester’s InterWeave sys- tem allows the programmer to map shared segments into programs spread across heterogeneous, distributed machines. InterWeave represents a merger and exten- sion of our previous Cashmere and InterAct projects, combining hardware co- herence within small multiprocessors, Cashmere-style lazy release consistency within tightly coupled clusters, and InterAct-style version-based consistency for distributed shared segments. In InterWeave, each shared segment evolves through a series of consistent ver- sions. When beginning a read-only critical section on a given segment, Inter- Weave uses a programmer-specified predicate to determine whether the currently cached version, if any, is “recent enough” to use. Inter-segment consistency is maintained by means of hashed vector timestamps. Automatic data conversions allow each program to employ its own natural data format, byte order, and align- ment, with full support for intra- and inter-segment pointers. Timestamping is used to determine and communicate only those pieces of a segment that are dif- ferent from the cached copy. A preliminary implementation of InterWeave is currently running on our Al- phaServer cluster. Driving applications include data mining, intelligent distributed environments, and scientific visualization.
