Single Pair Ethernet (SPE) standard implementations offer simplified cabling requirements tailored to specific application domains. Currently, 100BASE-T1, 10BASE-T1L, and 10BASE-T1S are the SPE standards that have gained some acceptance. Unfortunately, the time synchronization performance of SPE is in question, especially for the 10 Mb/s variants, as the Physical Layer (PHY) uses low signaling rate, complex coding, and digital signal processing; furthermore, 10BASE-T1S also offers multidrop, half-duplex communication services. Our paper introduces a modular hardware solution for SPE performance evaluation utilizing Microcontrollers (MCU) and the flexPTP MCU Precision Time Protocol (PTP) implementation. We investigate the standard 100BASE-TX Ethernet and compare it to the automotive 100BASE-T1, 10BASE-T1S, and the long-range industrial 10BASE-T1L Ethernet with a PI and a Kalman filter servo algorithm. Our investigation shows that 100BASE-T1 offers significantly better accuracy and precision than the others; 100BASE-TX follows it in performance, and the 10BASE-T1L and 10BASE-T1 offer the worst timing performance.
Neuromorphic accelerators, whether asynchronous meshes or globally-asynchronous, locally synchronous (GALS) fabrics, usually devote die area to barrier synchronizers, finely tuned clock trees, and metastability filters to keep spikes in lock-step. How much of that circuitry is truly indispensable? We quantify the intrinsic jitter tolerance of spiking neural networks (SNNs) and show how to push this tolerance further. We introduce a clock offset injector, a single GPU tensor op that time-shifts each core’s spikes by an arbitrary delay, and allows any PyTorch SNN to be stress-tested or hardened without code changes. Vision (N-MNIST) and audio (Spiking Heidelberg Digits) models, trained with and without our proposed offset-aware augmentation, are evaluated across nine skew levels (0-50% of the sample window) and up to eight cores. Baseline N-MNIST stays within ±1 percentage points (pp) until skew reaches 18 ms (6.1%). By accounting for temporally misaligned spikes during training time, we extend survival to 46 ms. Timing-critical SHD collapses beyond 23 ms (9%) but regains 6-9 pp after augmentation. These numbers map out safe envelopes for clock simplification: vision-only workloads can tolerate ≈ 3 ms per hop, while mixed vision-audio workloads must hold skew below 2 ms, or depend on timing-offset aware training. This ultimately shows how to enable lower-effort clocking and using software-level mitigation when needed.
A time transfer link consisting of PTP High Accuracy equipment (PTP-HA, e.g., White Rabbit) can transfer time with sub-nanosecond accuracy. Originally PTP-HA equipment is calibrated as a set of two devices. Progress in calibration makes exchange of individual components, such as pluggable transceivers, possible without the need for expensive in-situ end-to-end calibrations. This is expected to be covered in a future release of the IEEE 1588 standard.To determine the latencies of a pluggable transceiver, a time delay calibrated reference photodetector is essential. Latency values are stored in the transceiver memory, which enables exchange without breaking calibration.This paper describes the results of inter-comparing several calibrated reference photodetectors that were calibrated in different calibration setups. These photodetectors were exchanged between laboratories to cross-verify their stated optical to electrical time delays. The initial cross-verification results lead to further investigation of the calibration setup. The results of this investigation will be reported.
Measuring the performance of one-sided and collective operations on a set of distributed resources is not trivial because of the complexity of distributed time measurement on non-synchronized hardware. Simulation is attractive because distributed applications can be executed on a controlled set of resources and in a reproducible manner. Writing a fully calibrated simulator for a new software library represents however a time- and labor-intensive effort that is usually only undertaken for well established software solutions such as the MPI standard.This paper introduces an approach leveraging the SimGrid simulation framework for the study of an existing standard for high-performance computing parallel applications, featuring one-sided communications and atomic and collective operations. We present the several mechanisms that are mandatory to integrate the behavior of the real distributed applications into the simulated platform. Leveraging this simulation framework greatly simplifies this endeavor, opening the way to the study of more distributed middleware and libraries through realistic simulations.
IEEE 802.1AS and time-sensitive networks are becoming increasingly widespread and serve as the basis for scheduled traffic or sequence of events in industrial networks. The moment a fault occurs in a TSN network, troubleshooting is laborious and expensive. To mitigate the expenses and duration of troubleshooting, it is imperative to implement monitoring, fault detection and diagnosis, and root cause analysis. Decentralized expert knowledge is the sole source of information regarding symptoms, potential faults, and causes. Knowledge graphs are used in various disciplines, including network troubleshooting, to share knowledge of specific domains. At present, there is no methodical troubleshooting assistant for IEEE 802.1AS. The current methods for monitoring, diagnosis, and fault analysis in networks and time synchronization are comprehensively examined in this paper. In addition, it gives an ontology, possible symptoms, faults, and root causes, as well as an IEEE 802.1AS knowledge graph for fixing problems. A test setup is then used to implement and assess the knowledge graph that has been created. This work establishes the foundation for a shared knowledge base for root-cause analysis in IEEE 802.1AS networks, which requires further development to minimize the time and expenses associated with troubleshooting.
This paper presents a comparative study of three high-resolution digital phase measurement methods for sub-nanosecond synchronization over Ethernet networks. Implemented in modern FPGAs, the Digital Dual Mixer Time Difference (DDMTD), Time-to-Digital Converter (TDC), and PLL-based Counter (PLLCTR) circuits are evaluated in terms of accuracy, resolution, and implementation complexity. The measurements were validated using a calibrated 12 GHz oscilloscope. Results show that all three methods achieve sub-100 ps residual error, with the DDMTD offering the highest precision and the TDC providing flexibility for non-periodic signals. The PLLCTR delivers compact, fast measurements with moderate resolution. The findings support the DDMTD’s suitability for applications like White Rabbit, while the TDC and the PLLCTR offer broader applicability for highly accurate, FPGA-based clock synchronization systems.
White Rabbit enhances the IEEE 1588 Precision Time Protocol (PTP) by integrating Layer-1 synchronization akin to Synchronous Ethernet (SyncE) and physical-layer delay calibration to achieve sub-nanosecond synchronization. To ensure the accuracy of the synchronization with minimal uncertainty, measuring the absolute time delay between optical and electrical (OE) reference planes is vital to achieve absolute calibration of the White Rabbit system. This work seeks to replicate the Mach-Zehnder modulator (MZM) method documented by Peek et.al, capable of achieving an uncertainty as low as two picoseconds, enables precise time-delay characterization in optical transceivers. Investigations into the robustness of the measurement is pursued with the goal of repeatable measurements. The outcomes of these validations are expected to contribute significantly to advancements in time-transfer technologies and independent absolute calibration for time-distribution equipment.
Education and research of precision clock synchronization are limited by the availability of low-cost, open hardware and software devices, especially the lack of such grandmaster clocks (GMC). The paper introduces the second iteration of our low-cost GMC to solve this problem, which is based on the Beaglebone Black (BBB) single-board computer (SBC). SBCs consist of system-on-a-chip (SoC) devices, which integrate application processor cores (mainly ARM Cortex-Ax cores), network interfaces, and embedded peripherals, such as timers, I2C bus controllers, etc. Our primary aim is to implement the GMC only with the available peripherals of the SoC, except for a reference oscillator and a GNSS receiver. Selection of the reference oscillator and the GNSS receiver is also driven by price constraints, as the solution does not want to compete with commercial devices. On the contrary, it wants to let researchers, educators, and even students rebuild the device at low cost and start the experimentation with time synchronization-related concepts. The solution comprises a simple prototype CAPE (extension board for the Beaglebone platform) and software components. The paper presents the requirements, design decisions, improvements in hardware and software, and closes with an initial performance evaluation.
Accurate time recovery and clock synchronization are crucial for achieving high-contrast astronomical images using the recently proposed "Optical Aperture Synthesis" (OAS) method, which utilizes photonic integrated circuits (Photo-IC) to align the phases of photons captured by multiple optical sub-apertures/telescopes. In this method, the modulated optical signal from an artificial laser guide star serves as the global phase reference for each sub-aperture/telescope. After this optical signal is converted to an electrical signal and sampled, a digital signal processing (DSP) system processes the modulated signal to suppress excess jitter and accurately measures the phase offset caused by various factors such as atmospheric fluctuations and instrumentation non-idealities. Control signals derived using these phase estimates are fed back to the Photo-IC to correct for the phase variations for all sub-apertures/telescopes. Although numerical simulations showed that the proposed DSP system is possibly accurate enough to recover the phase variations, early measurements showed that temperature variations are detrimental to the stability of the analog signal chain.
A methodology for assessing the conformance of clock control systems with respect to IEC/IEEE 60802 using parameter estimation is presented. The input signal to the DUT is acquired by capturing the incoming gPTP messages. Two methods to capture the output signal are presented: One approach uses the offset From Time Transmitter logged for debugging, and the other uses the 1PPS signal and reconstructs the output signal with a sampling rate at 8 Hz, by using the equivalent-time sampling approach. The parameter estimation is conducted in two steps: The first uses a broad excitation to determine the order of the model, and the second uses an adaptive excitation to obtain a precise estimate to assess the conformance using the estimated model. Measurements performed show that a precise estimate is obtained.
Accurate timestamping in LoRa networks is very important for time synchronization and localization applications. However concurrent transmissions, especially those with different Spreading Factors (SFs), can cause distortions during the phase of the preamble detection, which could make the time of arrival timestamp less accurate, and thus, affecting the final synchronization. This paper deploys a MATLAB-based simulation framework to evaluate the robustness of timestamp process under these conditions. In particular, the paper focuses on inter-SF interference by simulating the reception of overlapping LoRa preamble and measuring the resulting error in the identification of the Start-of-Frame Delimiter (SFD), which is the reference point for timestamp the arrival of a LoRa packet. Simulations explore the impact of several parameters, including the noise introduced by the communication channel, the asynchrony of the incoming LoRa signal with the respect to the clock of the baseband Analog to Digital Converter (ADC), and the presence of interfering signals at SF9 and SF12. The results demonstrate that the timestamp jitter (for SF7) stays below 2 μs when the SNR due to the communication channel is 0 dB or higher and no concurrent transmission. However, when inter-SF transmissions occur at the same time, the timestamp jitter increases, especially at high SNR levels where the inter-SF interference is stronger than the noise. Additionally, SF12 interferers cause less timestamp error than SF9 ones due to greater spectral separation with respect to SF7. The results demonstrate that the preamble structure of LoRa allows for microsecond synchronization accuracy even in adverse conditions, with greater robustness achieved by leveraging SF diversity.
Achieving precise time synchronization in wireless systems is essential for both industrial applications and 5G, where sub-microsecond accuracy is required. However, since the Industrial Internet of Things (IIoT) market is negligible compared to the consumer electronics market, the so-called IIoT enhancements have not yet been implemented in silicon. Moreover, there is no guarantee that this situation will change soon. Thus, alternative solutions must be explored. This paper addresses this challenge by introducing a scheme that uses a protocol capable of leveraging existing infrastructure to synchronize User Equipments (UEs), with one of the UEs serving as the master. If this master is connected via a wired link to the factory network, it can also function as a boundary clock for the factory network, including any Time-Sensitive Networking (TSN) network. Furthermore, the 5G Core Network (5GC) and 5G Base Station (gNB) can also be synchronized if they are connected either to the factory network or to the master UE. The proposed solution is implemented and evaluated on a hardware testbed using OpenAirInterface (OAI) and Software Defined Radios (SDRs). Time offset and clock skew are analyzed using a moving average filter with various window sizes. Results show that a filter size of 1024 provides the best accuracy for offset prediction between UEs. In a controlled lab environment, the approach consistently achieves synchronization within +/-50 ns, leaving sufficient margin for synchronization errors in real deployments while still maintaining sub-microsecond accuracy. These findings demonstrate the feasibility and high performance of the proposed protocol for stringent industrial use cases.
The Precision Time Protocol (PTP), standardized as IEEE 1588, provides sub-microsecond synchronization across distributed systems and underpins critical infrastructure in telecommunications, finance, power systems, and industrial automation. While prior work has extensively analyzed PTP's vulnerability to network-based attacks, prompting the development of cryptographic protections and anomaly detectors, these defenses presume an uncompromised host. In this paper, we identify and exploit a critical blind spot in current threat models: kernel-level adversaries operating from within the host running the PTP stack. We present the first systematic study of kernel-rooted attacks on PTP, demonstrating how privileged attackers can manipulate system time by corrupting key interfaces without altering PTP network traffic. We implement three attack primitives, constant offset, progressive skew, and random jitter, using in-kernel payloads, and evaluate their impact on the widely used ptp4l and phc2sys daemons. Our experiments reveal that these attacks can silently destabilize clock synchronization, bypassing existing PTP security extensions. These findings highlight the urgent need to reconsider host-level trust assumptions and integrate kernel integrity into the design of secure time synchronization systems.
Accurate and precise time synchronization is critical in Smart Grid applications for accurate data collection, efficient energy distribution, and reliable system monitoring and control. Edge computing platforms have recently emerged as a promising solution for managing substantial amounts of data and computational requirements in a variety of application contexts, including Smart Grids. This approach allows for a reduction in the amount of information transmitted to the supervision systems of Distribution System Operators (DSO), a reduction in response latency, and an increase in overall system efficiency and reliability. This article provides an evaluation of various time synchronization protocols that can be implemented on the open-source edge computing framework Fledge, as well as the performance that can be achieved for smart grid applications. The Fledge framework has been deployed on a fan less industrial PC platform, equipped with network cards supporting in hardware the PTP protocol and the hardware timestamp of external events. The performance of various synchronization techniques commonly used in Smart Grids, such as Network Time Protocol (NTP), Precision Time Protocol (PTP), and Global Positioning System (GPS), was evaluated and compared. The results show that, while PTP has the highest precision and accuracy, NTP and GPS-based methods have better scalability.
Wireless clock synchronization approaches leveraging Internet of Things (IoT) could provide an inexpensive and scalable way to wirelessly distribute time between stable clock sources if time transfer clock errors are minimized and proper timing interfaces are created for IoT devices. Most IoT devices are focused on just providing reliable wireless Communications and do not expose the parameters and metrics needed to perform timing and ranging functionality from their transceivers. This paper explores developing an IoT device that adds timing and ranging functionality to an existing IoT device while maintaining its original communications capability. This is a hybrid architecture integrating an existing IoT transceiver with a stable clock source and an IoT I/Q transceiver to generate the parameters and metrics needed for wireless clock synchronization between IoT devices. This modified IoT device is known as a Timing, Communications, and Ranging Software Defined Radio (TCR-SDR) where timing and ranging functions are primary features being provided from SDR capabilities. SDR capabilities are providing by combining an IoT based I/Q transceiver with an FPGA and microcontroller. The current TCR-SDR is in a Receiver Carrier Board (RCB) form factor for exploring wireless clock synchronization algorithms with the Open Compute Project Timing Applications Project (OCP-TAP) Time Card. The OCP-TAP Time Card provides an open timing architecture and a source of time for data centers leveraging a GNSS receiver and a stable time reference (i.e. CSAC or TCXO) for holdover when GNSS signals are disrupted. In this paper we explore how to generate timing precision performance bounds of the TCR-SDR. This provides insights into performance limitations for distributing 10 MHz and 1 PPS reference sources from OCP-TAP Time Cards to other IoT devices. This discussion is focused on using LoRa to distribute the reference sources since LoRa is the IoT transceiver being used in the current TCR-SDR instantiation.
Datacenter environments are gaining an increasing presence in most technology sectors due to the progressive move of information systems to the cloud. The main drivers for this transition are the lower cost of operating in a shared infrastructure, the reliability and availability of public clouds and the convenience of a software-based management of the networking infrastructure.This trend is pushing the conversion from private clouds to public clouds for most non-regulated applications which do not require strict levels of performance or security. Hybrid clouds, where part of the infrastructure is deployed in private locations and interface with public clouds, or colocations within the datacenter are also common in sectors like finance, health or companies with strict cybersecurity or confidentiality requirements. Additionally, multiple distributed applications like telecom or utility networks have centralized their services in the datacenter while maintaining distributed access networks nationwide.Following the requirements of the applications with an increasing footprint in the datacenter, time synchronization needs have evolved in terms of accuracy, scalability, reliability and monitoring. In this paper, we present a novel technique which allows White Rabbit devices to measure the offset between their local synchronized clock and several distributed time sources with picosecond-level resolution leveraging their sub-nanosecond time synchronization accuracy.In order to demonstrate the unprecedent capabilities of this technique, the paper showcases multiple experiments where multiple White Rabbit and external Pulse Per Second and clock inputs are evaluated in the laboratory and in a real-life interconnection between two datacenters in a metro area.
As accurate and stable time transfer continues to increase its footprint across many market verticals, more so over convergence infrastructures such as data centers, applications such as 5G workloads, accurate packet scheduling, distributed databases, and synchronized collective communications may coexist. One of the key considerations is to further improve the overall performance of the Precision Time Protocol (PTP) by optimizing the control loop performance. This paper proposes a solution to assess optimal Proportional-Integral (PI) controller values using a Bayesian Optimization based method. We show a relative improvement of 12% in timing error, compared to the default parameters baseline.
This work addresses the calibration of asymmetry in optical transmission paths for precise time and frequency distribution. Specifically, we focus on calibrating White Rabbit technology, where local calibration is not possible due to the considerable distance between synchronized nodes. We developed an automatic calibration system using micro-electromechanical optical switches, which we verified under laboratory conditions. The verification process utilizes a basic calibration method, employing an auxiliary communication channel to transmit the 1PPS signal from a remote synchronized White Rabbit node for local comparison. The remote 1PPS signal’s transmission direction is time-multiplexed. Experimental results from a laboratory model of a real optical transmission system demonstrated the alignment between the automatic calibration system and our verification chain. The change in optical system asymmetry, simulated by adding additional optical fiber to the existing path, resulted in measured asymmetry changes of 101.5 ps by the automatic system and 102.6 ps by the verification chain. The overall difference between these two calibration methods was 1.1 ps. These findings confirm that the automatic system provides reliable results for calibrating asymmetry in optical transmission systems.
Network protocol analyzers are essential tools for professionals working in the field of Information and Communication Technology (ICT) for evaluation, monitoring, and troubleshooting purposes. Network protocol analyzers may use regular network adapters or specialized, dedicated capture hardware to collect information from the network, or they can be specialized devices. The task of network timing performance evaluation and monitoring is solved by specialized devices today, primarily due to the precision and accuracy requirements present in the application fields. However, as network timing matures and finds its applications in various fields using only specialized and also expensive devices cannot be sustained, lower cost, flexible solutions to the performance evaluation and monitoring problem must be developed. This paper investigates how regular, commercial of-the-shelf network adapters with network timing (HW timestamping, etc.) support can be applied for network timing evaluation and monitoring, investigates the system architecture options, lists implementation barriers and shows how to overcome them, and characterizes the performance limits of such solutions.
This paper describes an approach to PTP Server redundancy and the load balancing of PTP Clients in large scale datacenter applications. When a PTP Server fails, the PTP Clients that were synchronized to it are redistributed among the remaining operational PTP Servers. The redistribution is done in a way that the number of PTP Clients is load balanced as uniformly as possible across all the operational PTP Servers. The approach is part of the Simplified PTP (SPTP) protocol and is implemented through modifications of the Best timeTransmitter Clock Algorithm (BTCA) the Unicast timeTransmitter Table (UMT). These modifications are required because with the current IEEE Std 1588-2019 protocol, it is not possible for PTP Clients to consider a PTP Server differently.
