Massively parallel computers are built out of millions of devices, making the overall system's dependability too low. Fault-tolerant measures have thus to be included. This paper addresses network fault-tolerance. More specifically, a routing algorithm is developed that is able to isolate faulty units, entire nodes as well as single links, and to reroute messages to spares. The proposed method, based on multi-interval routing, is near optimal and requires only a few extra intervals.
A signature-based storage structure for nested tuples is proposed to efficiently evaluate queries including conditions of nested attributes in the nested relational databases. This method maintains a signa- ture with its pointer of the subrelation in the header part of the pages for each nested tuple. Using the subrelation signatures, nested predicates can be checked without accessing the subrelation, resulting in reduction of disk I/Os during query-processing steps.
This paper proposes a new scheduling algorithm, MART (Modification and Adjustment of Real-time Tasks), which can solve three problems for real-time scheduling. First, it can deal with two dynamic task changes: changes in the number of tasks and changes in task-timing characteristics. Second, it can keep the schedulability of all tasks by adjusting task periods when the system becomes overloaded due to the dynamic modifications mentioned above. Third, MART is similar to online scheduling algorithms, but it can analyze in advance the schedulability of a task set that should be scheduled. Therefore, using MART we can construct flexible systems that can adapt to a dynamically changing environment. MART is based on a well-established rate-monotonic scheduling algorithm, so the method of adjustment is easy and clear. The performance of the MART algorithm is supported by results from simulations.
A distributed fault-tolerant Convergence Function (CF) is proposed to resynchronize clocks with high precision. The CF can be used in conjunction with drift corrections which significantly increases the period between resynchronizations. This is important when clock drifts are large, because clock synchronization overhead then becomes intolerable. Clock differences are disseminated by a reliable message protocol after the clock valves are exchanged. All correct clocks then have identical copies of a matrix of clock differences. Matrix elements of correct clocks satisfy several relations. A subset of clocks that satisfy these relations defines an average clock. The influence of incorrect clocks on the average clock is shown to be bounded. The resynchronization is precise if clock reading errors are small, including uncertainties in transmission delays. Incorrect clocks may run too slow or too fast, exhibit omission failures or report inconsistent values
In this article we describe a programmable multi-processor system based on the Philips Video Signal Processor (VSP) for real-time video applications and the environment to program it. The main distinctive characteristic of this setup is the full programmability of both its computation and communication elements. Moreover, a versatile tool-set automates the programming of these elements. As a consequence, short design-cycles are achieved and the system is well suited for rapid prototyping. In this article we mainly concentrate on the design of the processing board of the system and the corresponding programming tool.
Presentation d'un modele de machine abstraite Prolog. Des debits concernant son implementation sont donnes
Rappel des strategies employees et discussion sur les recents resultats dans le domaine. La double exigence d'une haute performance et d'une grande tolerance aux fautes est examinee dans le contexte d'architectures multiprocesseurs a haute performance, y compris les systemes a technologie RISC
Description d'un systeme concu pour evaluer, developper et valider des interfaces orales homme-machine
Synthese generale sur l'utilisation des fibres optiques dans les reseaux locaux: composants utilises, configuration, tolerance aux fautes, etc.
Various network topologies are developed which have not appeared in the literature before which result in minimum diameter graphs for computer networks having connectivity four. The topologies presented have good survivability characteristics and result in more topologies being available for computer network designers which achieve the minimum diameter resulting in small transmission delays.
In general, microcomputer central processor devices are completely controllable from memory and memory control lines. By interjecting a controlling processor between the central processor chip and its memory, and using the central processor memory ready signal for synchronization, data can be supplied to the microprocessor either from an attached memory or from the controlling processor. The controlling processor may also download codes into the microprocessor's memory to be used either as programs or as data. By manipulating restart, hold and interrupt signal lines in addition to the memory lines, total control is achieved. Such a scheme can be used to orchestrate the simultaneous application of arrays of microcomputers to single large problems or to many discrete smaller problems. We describe the details of such connections to three commercially available devices: a Motorola 68000, an Advanced Micro Devices 29116 and a National Semiconductor NS32032 and indicate how our scheme may be used to connect such devices into a cooperating parallel array.
