Centrotherm photovoltaics AG is one of the first turn-key supplier of fabrication lines for the production of whole Cu(In, Ga)Se2 (CIGSe)-based thin-film modules of a size of ~1.5m2. A novel atmospheric pressure Se deposition process in combination with an atmospheric through-type furnace offers a very fast approach for CIGSe manufacturing [1]. Centrotherm Photovoltaics AG has set up, a unique laboratory-scale in-situ X-Ray diffraction (XRD) system allowing for the real-time investigation of the relevant phase formation processes [2]. This device is build around a small rapid thermal processing (RTP) furnace, mapping centrotherms large furnace atmospheric CIGSe-formation process to a laboratory scale. In this paper we will report on the systematic progress made in CIGSe RTP process design using this unique laboratory tool. The combined analysis of the phase evolution by insitu-XRD (i-XRD) and morphological studies (SEM) at defined reaction stages and corresponding EXD mappings leads to a concise understanding of the reaction process.
Sub-melt millisecond anneal (MSA) is one of major anneal techniques for forming ultra-shallow and highly activated junctions. Besides post-implant anneal for source/drain and source/drain extensions, MSA has also attracted increased interests in nickel-silicide formation recently. During the silicidation process, desired Ni diffusion in forming silicides is competing with un-wanted Ni diffusion along defects paths. The latter will cause higher junction leakage and/or source/drain leakage. Since the activation energy for the un-wanted diffusion is lower, higher process temperature with shorter duration is beneficial for minimizing the un-wanted diffusion. Furthermore, MSA allows high process temperature to be used for silicide formation, which can re-activate some dopants, such as arsenic and phosphors. These dopants are easily deactivated during lower temperature thermal processes post source/drain formation such as silicide block film deposition; therefore, transistor performance can be improved by using MSA for silicidation processes. In this work, dynamic surface annealing (DSA), which is one form of MSA techniques, was applied to form Ni-based silicides. The impacts of different combinations of soak RTA and DSA for thermal steps before and after selective nickel/NiSi strip were examined. One step DSA has been demonstrated effective reduction of Nickel piping by e-beam inspection count, improved NiSi resistance and junction leakage w/o device performance degradation.
The development of the MilliSecond Anneals (MSA) technology allows the use of short dwell time coupled with a high peak temperature in order to significantly reduce the global thermal budget. These points are fundamental in the phase transformation occurring in silicide materials: the high temperature allows the phase change and the short dwell time reduces the materials ability to diffuse and create electrical shorts and leakage. The main application using MSA for silicide steps is performed on Nickel or Nickel Platinum alloy, used in advance CMOS technology as 40 nm node and below. In this work, the capability of the Titanium to be silicided during millisecond anneal is compared to the performance of Rapid Thermal Processing (RTP) which has a high thermal budget above 750°C for few seconds. Full sheet sample are used to compare the phase formation of TiSi2 done either by RTP or by MSA process. The phase transition is followed by Rs measurement as function of the temperature and the created phases itself were characterised by XRD. The final goal of the study is to check the integration capability of Titanium silicide by MSA in a full process flow needing very low thermal budget.
We have studied n+ Si:C stressor formation by C or C7H7 ion implantation on blanket wafers for different integration schemes (so-called post Source/Drain versus post Source/Drain Extension integration). Using sheet resistance and High Resolution X-Ray Diffraction (HR-XRD) fitting parameters as the main metrics, we studied the influence of different implant/anneal parameters as well as the process sequence itself. For both integration schemes, suitable processing conditions were identified which result in acceptable sheet resistance and strain levels.
We present a physical based model for simulating the temperature and stress fields that incorporate full temperature and rate dependent thermal, optical and mechanical properties scanned laser spike annealing. We simulate the system in a 2D infinite line beam limit and a full 3D model including spatial variation of the laser intensity. These simulations accurately model effects of the finite laser beam size. Temperature profiles for narrow beam widths (3D) exhibit shorter tails and steeper gradients as compared to the 2D model. The impact of beam profiles and spatial fluctuations (noise) on the temperature uniformity is presented. Direct experimental measurements of temperature-time profiles from a narrow beam spike annealing system are used to calibrate and validate these models. The simulated thermal profiles were used as inputs in a finite element simulator (COMSOL) to determine the thermally induced stress fields. Resolved shear stress slip systems were determined as a function of anneal conditions (dwell and peak temperature).
A variety of processes based on radical oxidation (N 2 O/H 2 ) and spike RTO are investigated in this study to grow ultrathin SiO 2 layers. Their process space is mapped out to cover regimes of interest for gate-last or gate-first integration of high k dielectrics with metal gates. Applied's Centura RTP chamber is found to be readily compatible with the requirements associated with 22/20nm CMOS technology.
The earlier long-pulsed green laser annealing system had the big issue: a deep n-type layer, namely, a field stop (FS) layer in IGBT's structure was not sufficiently activated when thick wafers with large heat capacity were used. In order to cope with the big issue, we developed the thermal assist type annealing system in which a long-pulsed green laser (λ:515nm) was combined with a near infrared CW diode laser (λ:808nm). Advantages of the new annealing system are as follows: (1) The simultaneous activation of the B and P implant layers without interdiffusion of B and P dopants. (2) The deep activation of the P implant layer over a depth of 2um, applicable to changes in the wafer thickness of 100um to 525um. (3) The low thermal budget annealing to suppress the thermal damage caused by the temperature rise on the opposite side when the thin wafer is annealed. The newly developed laser annealing system can adapt more flexibly to the backside annealing for a wide variety of IGBT's applications.
High temperature RTO (Rapid Thermal Oxidation) process can get good quality but growth rate was too fast to get a controllable ultra-thin SiO2 as interfacial layer (IL) for high-K gate dielectrics application. In this paper, we investigated the physical and electrical properties of IL film obtained by different oxidation gas ratio, temperature, pressure. We found high temperature (>1080C) and hydrogen rich environment perform ultra-thin optical thickness (4A) while sustaining high quality characteristics. In accordance with Le Chatelier's principle, high hydrogen concentration drive SiO2 decomposed to SiO gas. Based on this method, we can demonstrate good quality IL and simultaneously optical thickness can be downscaled to achieve superior electrical performance. Hydrogen rich and high temperature SiO2 adding wet clean process with Hafnium-based high-K dielectrics demonstrate best compromising EOT 10A as well as 30% gate leakage reduction among the other condition.
This paper places focus on the special properties of pure boron chemical-vapor deposition (CVD) thin-film layers that, in several device applications, have recently been shown to augment the potentials of silicon device integration. Besides forming a reliable an efficient dopant source for both ultrashallow and deep p+n junctions, the deposited amorphous boron (α-B) layer itself, even for sub-nm thicknesses, is instrumental in suppressing minority electron injection from the n-region into the p+ contact. Therefore, even for nm-shallow junctions where the current levels mainly will approach high Schottky-like values, the diodes exhibit saturation current levels that can become as low as that of conventional deep junctions. Moreover, the α-B layer has chemical etch properties that make it particularly suitable for integration as the front-entrance window in photodiodes for detecting nm-low-penetration-depth radiation and charged particles.
Advanced millisecond annealing technologies are being implemented to enable scaling of silicidation of Ni for contacts. There are several aspects of the millisecond annealing process that must be optimized in order to minimize defects and improve yield. One critical aspect is that NiSi agglomeration must be suppressed at higher annealing temperatures. Typically, the onset of agglomeration can be detected by microscopic observation, phase analysis or electrical measurement. This paper describes an alternate approach using the Coherent Gradient Sensing (CGS) interferometer to provide a fast, non-contact method for quickly identifying the nickel silicide agglomeration threshold. Wafers with blanket Ni films were annealing using laser spike annealing (LSA) at various temperatures. The CGS technique is demonstrated to be sensitive to changes in surface morphology associated with the nickel silicide phase transitions and agglomeration and the results correlate to more conventional metrology approaches.
Shallow junction engineering drives the development of thermal processing manufacturing equipment. Junction depth and lateral source/drain extension doping profiles have an important impact on source/drain parasitic resistance and device short channel effects. These parameters were identified by ITRS as key processing steps. This work presents the result of a modeling study of lateral doping abruptness and its impact on device performance. The impact of lateral abruptness is examined from the point of view of on- and off-current, (Ion, Ioff). Ion, Ioff curves provide a way for complex comparing of device performance, including both power consumption and circuit performance (circuit delay). It is shown that threshold roll-off characteristics are degraded by a very abrupt lateral profile. The results of this study lead to the conclusion that benefits of the abrupt source/drain extension are overestimated.
Boron 200eV 1E15/cm2 p+ Ultra Shallow Junctions with various PAI (Ge, Xe & In) and HALO (As & Sb) implantation activated by msec laser annealing (1220°C to 1350°C) were studied using Junction Photo Voltage (JPV) and Modulated Photo Reflectance (MPR). JPV and MPR provided information about junction quality; dopant activation, junction capacitance, residual implant damage and junction leakage. Highest p+ junction quality and best p+ dopant activation was achieved with laser annealing temperatures >1300°C. The results with Sb-HALO were worse than with As-HALO. For HALO implants junction leakage was controlled by direct band to band tunneling while for no HALO it was controlled by end of range residual PAI defects. The high junction leakage (exceeding E-5 A/cm2) could lead to unreliable Rs and junction capacitance determination.
Arsenic, Phosphorus and Antimony dopants for n+ USJ formation was studied for junction quality comparing nonmelt to melt laser annealing without and with BF2 or In HALO structures. When junction leakage was high >2E-2A/cm2 no reliable sheet resistance could be determined. We observed between 21nm to 70nm of liquid phase dopant diffusion with the melt process and dopant activation levels were lower than expected due to the very short annealing and cool-down quenching rates with laser annealing requiring longer dwell times. Also, cold implants and C co-implants with laser annealing resulted in very high junction leakage as did the additional of either a BF2 or In HALO structure.
Throughout the history of rapid thermal processing the generation and subsequent elimination of crystalline slip has been an ongoing battle. The combination of high temperatures, temperature gradients, and strain rates typically present in RTP/RTA systems often result in the deformation of the silicon substrate which in turn, leads to problems with lithographic overlay. In recent years, the issue has become more troublesome as technologies continue to scale. A number of events have been documented at IBM where qualified, healthy machines have impacted process yield via the permanent (albeit subtle) deformation of product wafers. Even though a strong correlation between RTP, stress/slip, and overlay failure has been established in the past this work was an attempt to investigate the more subtle nature of recent events in an empirical and systematic fashion. To that end a multi-faceted study was conducted with three specific objectives; (1) to elucidate the relationship between process conditions and overlay failure, (2) to develop a robust automated measurement for stress/slip detection, and (3) to use those techniques and results as a basis from which to better define process windows and manufacturing control strategies. Results from this investigation indicated a critical dependence on pyrometer offset deltas at the wafer edge with values as small as +2C found to produce unacceptable levels of stress. In all cases, the temperature offset window was found to be ~ 10C wide with the exact location of the slip free conditions dependent on the particulars of the processes and the process chamber.
One of the most promising methods to improve the efficiency of crystalline solar cells is the implementation of so-called selective emitters. This is the decoupling of the requirements for the front doping for light conversion and metallization. Underneath the contact fingers, a high doping is chosen to insure a good ohmic contact, whereas in the photoactive area a light doping is employed to reduce recombination losses and increase quantum efficiency in the short wavelength region of the device. Besides using costly and lengthy masking processes, selective emitters can be produced using lasers by means of laser doping. A laser beam with a suitable wavelength with good absorption in silicon is focused to a spot size which matches the width of the contact fingers. In this paper the process is explained, results are presented which show that the targeted effect can be achieved without detrimental “side effects”, and an optical beam splitter technology for high throughput production is proposed.
Rapid thermal annealing in nitric oxide (RTNO) has long been used for the formation of ultrathin silicon oxynitride gate dielectrics. Nitric oxide (NO) furnace anneals are used in the formation of floating gate Flash memory transistor tunnel oxides. Nitrogen is thus, incorporated to improve the oxide reliability during program/erase cycling endurance and data retention. We present here a study of rapid thermal annealing and oxide growth in nitric oxide using Applied Materials single-wafer rapid thermal process (RTP) that enables the RTNO anneal to operate at higher temperatures compared to furnace, thereby allowing two times greater incorporation of nitrogen at the silicon/silicon dioxide interface. At 1200°C, a greater than 11% peak interface nitrogen concentration as measured by secondary ion mass spectroscopy (SIMS) in a 75 Angstrom SiON film is achieved. Reliability testing using a floating gate flash memory capacitor with minority carrier source (implants) test vehicle shows that this increase in the peak interface nitrogen results in an improvement in the tunnel oxide's program/erase cycling endurance and data retention. For future memory devices, for example 3D memory devices, the use of direct RTNO oxide growth for dielectric formations is possible. In this case, higher temperatures allow the growth of thicker oxides in pure NO at 1200°C, with greater nitrogen incorporation.
In order to investigate whether the performance of microbolometer based heat imaging devices can be improved by excimer laser annealing, we performed several experiments on amorphous silicon layers. Samples with unstructured and structured amorphous silicon layers, which are fabricated with different doping concentrations using a plasma enhanced chemical vapor deposition process, are annealed with Krypton Fluoride excimer laser light at various energy densities. The samples are then electrically analyzed to verify laser annealing. They are also characterized in terms of their electrical conductivity, their temperature coefficient of electrical resistance and their 1/f noise as a function of energy density of the laser. The measurements are used to discuss whether excimer laser annealing is of use to improve microbolometer performance. A threshold value for the energy density at which recrystallization caused by laser irradiation occurs is observed to be 100 mJ/cm2 for both structured and unstructured samples. The temperature coefficient of electrical resistance decreases with increasing energy density from a value of 2%K-1 down to a value of approximately 0.9%K-1.
We studied pulsed laser induced epitaxy of silicon using a seeding wafer to realize location-and orientation-control of silicon grain. Silicon grains as large as 4 µm × 4 µm with mostly the preferred (100) orientation area were obtained on top of contact openings through SiO2 to seeding silicon (100) wafer. The orientation of the seed is inherited by a-Si during the solidification phase of molten-Si. The maximum process temperature of this process is 545 °C which is for LPCVD deposition of a-Si. This layer is suitable for high mobility SOI CMOS devices which serve as building blocks for monolithic 3D integration.
Nickel silicide is a common contact material for current generation microelectronic devices. As the technology nodes become smaller, forming the NiSi phase with milli-second or below annealing is an attractive alternative to conventional RTA annealing because of the potential for increased device performance and yield. This paper will discuss the use of a dual beam laser spike annealing (LSA) to form nickel silicide on silicon wafers in the microsecond regime. A detailed evaluation of anneal times (400μs and 800μs) and anneal exposure (100% and 50% stitching, or single and double anneals) was done on 300mm wafers with NiPtSix film (post-RTA1 anneal/100Å). Analytical testing by sheet resistance, CGS, XRD, AES depth profile, AFM, SEM, and ellipsometry was performed on the wafers to examine the effects of anneal times and exposure on phase transition and/or film morphology. A study of the nickel silicide transition curve by sheet resistance vs. temperature shows that there is a higher NiSi damage threshold temperature for single anneal as compared to double anneal. For uniformly annealed full wafers processed at temperatures slightly below the damage threshold, the results confirm: 1) NiSi was formed with negligible or small differences in film structure and, 2) the 100% stitching single annealed wafers show similar process performance in terms of sheet resistance and within wafer uniformity to the 50% stitching double annealed wafers at both 400 and 800μs.
The application of lasers for annealing wafer-based and thin-film microelectronic devices is steadily increasing. Excellent control of material characteristics such as the dopant activation profile are achieved through proper selection of the laser parameters which directly influence the laser material interaction; these include wavelength, pulse duration and fluency. Nanosecond pulses at short UV wavelengths, as emitted by excimer lasers, are particularly beneficial for shallow activation and the increasing demand to keep the overall temperature budget low during the anneal. The short wavelength of e.g. 308nm or 248nm leads to an absorption depth of less than 10 nm in crystalline silicon that enables the deposition of the laser energy in a small confined volume. In this paper, we look at lasers, optics and annealing systems that have proved themselves in the annealing of semiconductor wafers. The application of a system for the uniform shallow activation of Back-Side-Illuminated (BSI) CMOS image sensors will be discussed in detail. This annealing system is based on a proven industrial excimer laser and yields a high uniformity of sheet resistance that is better than 0.5% (sigma). A unique optics system has been developed to provide a highly uniform thin line beam of 300 mm length. The wafer is covered in a single scan so that the process time for a 12" wafer is reduced to only 20 seconds. Results from recent application work involving dopant activation for silicon wafers will also be presented.
