This paper presents a storage scheme which statically assigns pixel/texel coordinates to multiple memory banks in order to minimize frame buffer and texture memory access load imbalance. In this scheme, the pixels stored in a particular memory bank are placed at the center and the vertices of hexagons packed in the frame buffer By making these hexagons close to regular so that the pixel placement is uniform and isotropic, frame buffer and texture memory accesses are evenly distributed over the memory banks. The analysis of memory access patterns in rendering typical 3D graphics scenes shows that the hexagonal storage scheme can reduce rendering performance degradation due to bank conflicts by an average of 10% compared to the traditional rectangular storage scheme.
Complex shaders must be partitioned into multiple passes to execute on GPUs with limited hardware resources. Automatic partitioning gives rise to an NP-hard scheduling problem that can be solved by any number of established techniques. One such technique, Dynamic Programming (DP), is commonly used for instruction scheduling and register allocation in the code generation phase of compilers. Since automatic partitioning occurs during the shader compilation process it is natural to ask whether DP is useful for shader partitioning as well as for code generation. This paper demonstrates that these problems are Markovian and can be solved by DP techniques. It presents a DP algorithm for shader partitioning that can be adapted for use with any GPU architecture. Unlike solutions produced by other techniques DP solutions are globally optimal. Experimental results on a set of test cases with a commercial prerelease compiler for a popular high level shading language showed a DP algorithm had an average runtime cost of O(n1.14966) which is less than O(n log n) on the region of interest in n. This demonstrates that efficient and optimal automatic shader partitioning can be an emergent byproduct of a DP-based code generator for a very high performance GPU.
Many recent publications have shown that a large variety of computation involved in computer graphics can be moved from the CPU to the GPU, by a clever use of vertex or fragment shaders. Nonetheless there is still one kind of algorithms that is hard to translate from CPU to GPU: mesh refinement techniques. The main reason for this, is that vertex shaders available on current graphics hardware do not allow the generation of additional vertices on a mesh stored in graphics hardware. In this paper, we propose a general solution to generate mesh refinement on GPU. The main idea is to define a generic refinement pattern that will be used to virtually create additional inner vertices for a given polygon. These vertices are then translated according to some procedural displacement map defining the underlying geometry (similarly, the normal vectors may be transformed according to some procedural normal map). For illustration purpose, we use a tesselated triangular pattern, but many other refinement patterns may be employed. To show its flexibility, the technique has been applied on a large variety of refinement techniques: procedural displacement mapping, as well as more complex techniques such as curved PN-triangles or ST-meshes.
We present a vertex compression technique suitable for efficient decompression on graphics hardware. Given a user-specified number of bits per vertex, we automatically allocate bits to vertex attributes for quantization to maximize quality, guided by an image-space error metric. This allocation accounts for the constraints of graphics hardware by packing the quantized attributes into bins associated with the hardware's vectorized vertex data elements. We show that this general approach is also applicable if the user specifies a total desired model size. We present an algorithm that integrally combines vertex decimation and attribute quantization to produce the best quality model for a user-specified data size. Such models have an appropriate balance between the number of vertices and the number of bits per vertex.Vertex data is transmitted to and optionally stored in video memory in the compressed form. The vertices are decompressed on-the-fly using a vertex program at rendering time. Our algorithms not only work well within the constraints of current graphics hardware but also generalize to a setting where these constraints are relaxed. They apply to models with a wide variety of vertex attributes, providing new tools for optimizing space and bandwidth constraints of interactive graphics applications.
The growing application of user-defined programs within graphics processing units (GPUs) has transformed the fixed-function display pipeline into a largely programmable pipeline. In this paper we propose that the elements fed through the pipeline be made entirely procedural. To enable this, we present a modification of the conventional graphics processor in which all procedures are executed in a common processor array and the rasterizer is augmented with a more general sampling controller. By executing both the geometric and shading elements of a procedural graphics model in a single processor we retain the data amplification that distinguishes procedural descriptions without a corresponding explosion of external bandwidth.
High-quality off-line rendering requires many features not natively supported by current commodity graphics hardware: wide smooth filters, high sampling rates, order-independent transparency, spectral opacity, motion blur, depth of field. We present a GPU-based hidden-surface algorithm that implements all these features. The algorithm is Reyes-like but uses regular sampling and multiple passes. Transparency is implemented by depth peeling, made more efficient by opacity thresholding and a new method called z batches. We discuss performance and some design trade-offs. At high spatial sampling rates, our implementation is substantially faster than a CPU-only renderer for typical scenes.
Commodity graphics hardware has become increasingly programmable over the last few years but has been limited to fixed resource allocation. These architectures handle some workloads well, others poorly; load-balancing to maximize graphics hardware performance has become a critical issue. In this paper, we explore one solution to this problem using compile-time resource allocation. For our experiments, we implement a graphics pipeline on Raw, a tile-based multicore processor. We express both the full graphics pipeline and the shaders using StreamIt, a high-level language based on the stream programming model. The programmer specifies the number of tiles per pipeline stage, and the StreamIt compiler maps the computation to the Raw architecture.We evaluate our reconfigurable architecture using a mix of common rendering tasks with different workloads and improve throughput by 55-157% over a static allocation. Although our early prototype cannot compete in performance against commercial state-of-the-art graphics processors, we believe that this paper describes an important first step in addressing the load-balancing challenge.
In this paper we propose a hardware accelerated ray-casting architecture for multi-resolution volumetric datasets. The architecture is targeted at rendering very large datasets with limited voxel memory resources for both cases where the working set of a frame does or does not fit into the voxel memory. We describe the multi-resolution model used to organize the volume data, especially the wavelet based compression scheme. An efficient hardware implementation of the wavelet decompression is presented and the considerations for volume memory management are discussed. By incorporating the wavelet decompression in hardware a multiple of the decompression bandwidth compared to a PC can be achieved We also show that the impact of our multi-resolution scheme on the actual ray-casting pipeline is minimal.
We present a fast and energy-efficient z-comparator that takes advantage of the fact that the result of most depth comparisons can be determined by examining just a few bits. This feature is made possible by the use of asynchronous logic, which enables the comparator to rapidly compare bits until the result is clear and then stop. Using depth data from well-known computer games, SPICE simulations indicate that our comparator consumes only 25% of the energy and operates 1.67 times faster, on average, compared to an equivalent synchronous design. The comparator design is used to illustrate a more general design principle, "compute on demand," which can potentially enable graphics hardware to be faster and more energy-efficient.
We present a novel method for rendering shadow volumes. The core idea of the method is to locally choose between Z-pass and Z-fail algorithms on a per-tile basis. The choice is made by comparing the contents of the low-resolution depth buffer against an automatically constructed split plane. We show that this reduces the number of stencil updates substantially without affecting the resulting shadows. We outline a simple and efficient hardware implementation that enables the early tile culling stages to reject considerably more pixels than with shadow volume optimizations currently available in the hardware.
Modern graphics hardware architectures excel at compute-intensive tasks such as ray-triangle intersection, making them attractive target platforms for raytracing. To date, most GPU-based raytracers have relied upon uniform grid acceleration structures. In contrast, the kd-tree has gained widespread use in CPU-based raytracers and is regarded as the best general-purpose acceleration structure. We demonstrate two kd-tree traversal algorithms suitable for GPU implementation and integrate them into a streaming raytracer. We show that for scenes with many objects at different scales, our kd-tree algorithms are up to 8 times faster than a uniform grid. In addition, we identify load balancing and input data recirculation as two fundamental sources of inefficiency when raytracing on current graphics hardware.
We present a novel texture compression scheme, called iPACKMAN, targeted for hardware implementation. In terms of image quality, it outperforms the previous de facto standard texture compression algorithms in the majority of all cases that we have tested. Our new algorithm is an extension of the PACKMAN texture compression system, and while it is a bit more complex than PACKMAN, it is still very low in terms of hardware complexity.
Perlin noise is one of the primary tools responsible for the success of procedural shading in production rendering. It breaks the crisp computer generated look by adding apparent randomness that is controllable and repeatable. Both Perlin's original noise algorithm and his later improved noise were designed to run efficiently on a CPU. These algorithms do not map as well to the design and resource limits of the typical GPU. We propose two modifications to Perlin's improved noise that make it much more suitable for GPU implementation, allowing faster direct computation. The modified noise can be totally evaluated on the GPU without resorting to texture accesses or "baked" into a texture with consistent appearance between textured and computed noise. However, it is most useful for 3D and 4D noise, which cannot easily be stored in reasonably-sized textures. We present one implementation of our modified noise using computation or direct texturing for 1D and 2D noise, and a procedural combination of 2D textures for the 3D noise.
In this paper we describe the architecture of the 3D graphics LSI core for mobile phone "Z3D". The major 3D graphics applications on mobile phones are character animation and games. While a character animation or a game is running, the CPU has to be used for the communication to the center machine and CPU clock frequency is low. Therefore, the requirement of Z3D is small, low power, and CPU free. The pipeline of Z3D is composed of a geometry engine, rendering engine, and pixel engine. Generally, these modules run in pipeline on PC, but running in pipeline, power consumption rises. We used gated clock control for low power consumption and having the pipeline work in sequential, we could reduce 40% of the power consumption with 10% performance decreasing. The geometry processing performance of Z3D is up to 185Kvertex/sec and the pixel performance is 5Mpixel/sec. This performance is enough to have character animations and games run. The data of 3D shape and animation can be defined using common 3D modeler and contents program can be described by Java. Low level rendering interface and animation rendering interface are provided as a Java API. All the contents programs can be downloaded from network.
This paper presents a new, lossy texture compression technique that is suited to implementation on low-cost, low-bandwidth devices as well as more powerful rendering systems. It uses a representation that is based on the blending of two (or more) 'low frequency' signals using a high frequency but low precision modulation signal. Continuity of the low frequency signals helps to avoid block artefacts. Decompression costs are kept low through use of fixed-rate encoding and by eliminating indirect data access, as needed with Vector Quantisation schemes. Good quality reproduction of (A)RGB textures is achieved with a choice of 4bpp or 2bpp representations.
We show how a future graphics processor unit (GPU), enhanced with random read and write to video memory, can represent, refine and adjust complex meshes arising in modeling, simulation and animation. To leverage SIMD parallelism, a general model based on the mesh atlas is developed and a particular implementation without adjacency pointers is proposed in which primal, binary refinement of, possibly mixed, quadrilateral and triangular meshes of arbitrary topological genus, as well as their traversal is supported by user-transparent programmable graphics hardware. Adjustment, such as subdivision smoothing rules, is realized as user-programmable mesh shader routines. Attributes are generic and can be defined in the graphics application by binding them to one of several general addressing mechanisms.
Current graphics hardware can render procedurally shaded objects in real-time. However, due to resource and performance limitations, interactive shaders can not yet approach the complexity of shaders written for film production and software rendering, which may stretch to thousands of lines. These constraints limit not only the complexity of a single shader, but also the number of shaded objects that can be rendered at interactive rates. This problem has many similarities to the rendering of large models, the source of extensive research in geometric simplification and level of detail. We introduce an analogous process for shading : shader simplification. Starting from an initial detailed shader, shader simplification automatically produces a set of simplified shaders or a single new shader with extra level-of-detail parameters that control the shader execution. The resulting level-of-detail shader can automatically adjust its rendered appearance based on measures of distance, size, or importance, as well as physical limits such as rendering time budget or texture usage. We demonstrate shader simplification with a system that automatically creates shader levels of detail to reduce the number of texture accesses, one common limiting factor for current hardware.
We capitalize on recent advances in modern programmable graphics hardware, originally designed to support advanced local illumination models for shading, to instead perform two different kinds of global illumination models for light transport. We first use the new floating-point texture map formats to find matrix radiosity solutions for light transport in a diffuse environment, and use this example to investigate the differences between GPU and CPU performance on matrix operations. We then examine multiple-scattering subsurface light transport, which can be modeled to resemble a single radiosity gathering step. We use a multiresolution meshed atlas to organize a hierarchy of precomputed subsurface links, and devise a three-pass GPU algorithm to render in real time the subsurface-scattered illumination of an object, with dynamic lighting and viewing.
The Fourier transform is a well known and widely used tool in many scientific and engineering fields. The Fourier transform is essential for many image processing techniques, including filtering, manipulation, correction, and compression. As such, the computer graphics community could benefit greatly from such a tool if it were part of the graphics pipeline. As of late, computer graphics hardware has become amazingly cheap, powerful, and flexible. This paper describes how to utilize the current generation of cards to perform the fast Fourier transform (FFT) directly on the cards. We demonstrate a system that can synthesize an image by conventional means, perform the FFT, filter the image, and finally apply the inverse FFT in well under 1 second for a 512 by 512 image. This work paves the way for performing complicated, real-time image processing as part of the rendering pipeline.
This paper presents a cache-based memory architecture for volume graphics. We describe the memory organization and cache logic to implement a voxel cache based on 43 voxel blocks. We show an efficient prefetching scheme that increases the cache hit ratio to more than 98% in most cases. The performance of the memory system with different types of external memory is demonstrated by a cycle accurate C++ simulation. The VoxelCache memory architecture is designed to be easily adapted to different memory technologies, because all volume graphics specific parts of the memory system are encapsulated inside the on-chip cache. The design is targeted at implementation on off-the-shelf reconfigurable hardware.
